IS43LR16320B-6BL - 日耀电子 | ISSI/蕊成授权代理

容量	512M
規格	32Mx16
腳位/封裝	BGA(60)
電壓	1.8V
刷新	8K
字數	32M
型號別	IBIS, IBIS(46)
焊接	SnAgCu
狀態	Prod
類型	MDDR
總線寬度	16 = x16
速度（MHz）	up to 166Mhz
温規	Commercial Grade (0C to +70°C)
代/版本	B
產品系列	43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
温度等级	blank = Commercial Grade (0°C to +70°C)
焊料類型	L = SnAgCu
字數	320 = 32M
Generation	B = B
速度	6 = 166MHz
工作電壓範圍	LR = 1.8V mobile DDR (LPDDR)
腳位/封裝	B = BGA

數據表

索取報價

IS43LR16320B-6BL 特徵

JEDEC standard 1.8V power supply.
VDD = 1.8V, VDDQ = 1.8V
Four internal banks for concurrent operation
MRS cycle with address key programs
- CAS latency 2, 3 (clock) - Burst length (2, 4, 8, 16) - Burst type (sequential & interleave)
Fully differential clock inputs (CK, /CK)
All inputs except data & DM are sampled at the rising edge of the system clock
Data I/O transaction on both edges of data strobe
Bidirectional data strobe per byte of data (DQS)
DM for write masking only
Edge aligned data & data strobe output
Center aligned data & data strobe input
64ms refresh period (8K cycle)
Auto & self refresh
Concurrent Auto Precharge
Maximum clock frequency up to 166MHZ
Maximum data rate up to 333Mbps/pin
Power Saving support - PASR (Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - Deep Power Down Mode - Programmable Driver Strength Control by Full Strength or 1/2, 1/4, 1/8 of Full Strength
LVCMOS compatible inputs/outputs

概觀

The IS43/46LR16320B is a 536,870,912 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 8,388,608 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 16bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS.