IS43LR16128B-5BL-TR

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容量	2G
規格	128Mx16
電壓	1.8V
類型	MDDR
刷新	8K
狀態	Contact
腳位數	BGA(60)
速度Mhz	200, 166
評論上一篇
產品系列	43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
温度等级	blank = Commercial Grade (0°C to +70°C)
焊料類型	L = SnAgCu
字數	128 = 128M
Generation	B = B
速度	5 = 200MHz
工作電壓範圍	LR = 1.8V mobile DDR (LPDDR)
總線寬度	16 = x16
腳位/封裝	B = BGA
外包裝	Tape on Reel

IS43LR16128B-5BL-TR 特徵

JEDEC standard 1.8V power supply.
64ms refresh period (8K cycle)
VDD = 1.8V, VDDQ = 1.8V
Auto & self refresh
Four internal banks for concurrent operation
Concurrent Auto Precharge
MRS cycle with address key programs
Maximum clock frequency up to 208MHZ
- CAS latency 2, 3 (clock) - Burst length (2, 4, 8, 16) - Burst type (sequential & interleave)
Fully differential clock inputs (CK, /CK)
Maximum data rate up to 416Mbps/pin
Power Saving support
- PASR (Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh)
All inputs except data & DM are sampled at the rising
- Deep Power Down Mode edge of the system clock - Programmable Driver Strength Control by Full Strength
Data I/O transaction on both edges of data strobe or 1/2, 1/4, 1/8 or 3/4 of Full Strength
Bidirectional data strobe per byte of data (DQS)
Status Register Read (SRR)
DM for write masking only
LVCMOS compatible inputs/outputs
Edge aligned data & data strobe output
Operation Temperature:
- Commercial (TA= 0 ~ 70 C ) - Industrial (TA= -40 ~ 85 C ) - Automotive, A1 (TA= -40 ~ 85 C ) - Automotive, A2 (TA= -40 ~ 105 C )
Center aligned data & data strobe input OPTIONS
Configuration:
- 128Mx16 (32M x16 x 4 banks) - 64Mx32 (16M x32 x 4 banks)