| 容量 | 4G |
|---|---|
| 規格 | 128Mx32 |
| 電壓 | 1.2/1.8V |
| 類型 | LPDDR2 |
| 刷新 | 8K |
| 狀態 | Prod |
| 腳位數 | PoP(168) |
| 速度Mhz | 533, 400, 333 |
| 評論上一篇 | |
| 產品系列 | 43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade |
| 温度等级 | blank = Commercial Grade (0°C to +70°C) |
| 焊料類型 | L = SnAgCu |
| 字數 | 128 = 128M |
| Generation | A = A |
| 速度 | 25 = 400MHz |
| 工作電壓範圍 | LD = 1.2V - 1.8V LPDDR2 |
| 總線寬度 | 32 = x32 |
| 腳位/封裝 | BP = PoP BGA |
Clock: CK and CK# are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled on both positive and negative edge of CK. Single Data Rate (SDR) inputs, CS# and CKE, are sampled at the positive Clock edge. Clock is defined as the differential pair, CK and CK#. The positive Clock edge is defined by the crosspoint of a rising CK and a falling CK#. The negative Clock edge is defined by the crosspoint of a falling CK and a rising CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and therefore device input buffers and output drivers. Power savings modes are entered and exited through CKE transitions. CKE is considered part of the command code. See Command Truth Table for command code descriptions. CKE is sampled at the positive Clock edge. Chip Select: CS# is considered part of the command code. See Command Truth Table for command code descriptions. CS# is sampled at the positive Clock edge. DDR Command/Address Inputs: Uni-directional command/address bus inputs. CA is considered part of the command code. See Command Truth Table for command code descriptions. Data Inputs/Output: Bi-directional data bus.