1. 矽成
2. Mobile DRAM
3. 低電壓/移動SDR SDRAM
4. 低電壓SDR SDRAM
5. 2.5V
6. 256M 32Mx8
7. TSOP
8. IS45R83200J-75TLA1

IS45R83200J-75TLA1 特徵

• Clock frequency: 133, 100 MHz
• Fully synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Single Power supply: 2.5V + 0.2V
• LVTTL interface
• Programmable burst length
• • (1, 2, 4, 8, full page)
• Programmable burst sequence: Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh
• 8K refresh cycles every 32 ms (A2 grade) or 64 ms (commercial, industrial, A1 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command OPTIONS
• Package: 54-pin TSOP-II 54-ball BGA

概觀

ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows.