規格 16Mx16
類型 SDR
電壓 2.5V
刷新 8K
速度(MHz) 75 = up to 133Mhz @ CL2
腳位/封裝 T = TSOP
狀態 Prod
產品系列 45 = 車規SDRAM
總線寬度 16 = x16
字數 160 = 16M
代/版本 J
焊接 L = 100% matte Sn
温規 A1 = 車規 (-40C to +85°C)
外包裝 卷轴包

IS45R16160J-75TLA1-TR 特徵

  • Clock frequency: 133, 100 MHz
  • Fully synchronous; all signals referenced to a positive clock edge
  • Internal bank for hiding row access/precharge
  • Single Power supply: 2.5V + 0.2V
  • LVTTL interface
  • Programmable burst length
    • (1, 2, 4, 8, full page)
  • Programmable burst sequence: Sequential/Interleave
  • Auto Refresh (CBR)
  • Self Refresh
  • 8K refresh cycles every 32 ms (A2 grade) or 64 ms (commercial, industrial, A1 grade)
  • Random column address every clock cycle
  • Programmable CAS latency (2, 3 clocks)
  • Burst read/write and burst read/single write operations capability
  • Burst termination by burst stop and precharge command OPTIONS
  • Package: 54-pin TSOP-II 54-ball BGA

概觀

ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows.