容量 128M
規格 16Mx8
電壓 1.7-1.95V
速度(MHz) 166
腳位/封裝 BGA(24)
狀態 Prod
產品系列 66 = Pseudo SRAM
電壓範圍 ALL = 1.65V to 2.2V
焊接 L = 無鉛
温規 I = 工業級 (-40C to +85°C)

IS66WVH16M8ALL-133B2LI 特徵

  • 3.0V I/O, 11 bus signals
    • Single ended clock (CK)
  • 1.8V I/O, 12 bus signals
    • Differential clock (CK, CK#)
  • Chip Select (CS#)
  • 8-bit data bus (DQ[7:0])
  • Read-Write Data Strobe (RWDS)
    • Bidirectional Data Strobe / Mask
    • Output at the start of all transactions to indicate refresh latency
    • Output during read transactions as Read Data Strobe
    • Input during write transactions as Write Data Mask
  • RWDS DCARS Timing
    • During read transactions RWDS is offset by a second clock, phase shifted from CK
    • The Phase Shifted Clock is used to move the RWDS transition edge within the read data eye Performance Summary High Performance
  • Up to 333MB/s
  • Double-Data Rate (DDR) - two data transfers per clock
  • 166-MHz clock rate (333 MB/s) at 1.8V VCC
  • 100-MHz clock rate (200 MB/s) at 3.0V VCC
  • Sequential burst transactions
  • Configurable Burst Characteristics
    • Wrapped burst lengths:
    • 16 bytes (8 clocks)
    • 32 bytes (16 clocks)
    • 64 bytes (32 clocks)
    • 128 bytes (64 clocks)
    • Linear burst
    • Hybrid option - one wrapped burst followed by linear burst
    • Wrapped or linear burst type selected in each transaction
    • Configurable output drive strength

概觀

The IS66/67WVH16M8ALL/BLL are integrated memory device of 128Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 16M words by 8 bits. The device is a dual die stack of two 64Mb die. The device supports a HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation, designed specially for Mobile and Automotive applications.