容量 1G
類型 x1, x2, x4
電壓 3.3V
频率 104Mhz
温規 -40 to 105°C
腳位/封裝 16-SOIC, 8-WSON
狀態 Prod

IS37SML01G1-LLI 特徵

  • Efficient Read and Program modes
  • - Support SPI-Mode 0 and SPI-Mode 3 - Bus Width: x1, x2(1), x4 - Command Register Operation - NOP: 4 cycles - OTP Operation - Bad-Block-Protect - Boot Read
  • Advanced Security Protection
  • - Hardware Data Protection - Program/Erase Lockout during Power Transitions
  • Industry Standard Pin-out & Packages
  • - M =16-pin SOIC 300mil - L = 8-contact WSON 8x6mm Note: 1. X2 Program Operation is not defined. 2. Call Factory
  • Flexible & Efficient Memory Architecture
  • - Organization: - Memory Cell Array: (128M + 4M) x 8bit - Data Register: (2K + 64) x 8bit - Page Size: (2K + 64) Byte - Block Erase: (128K + 4K) Byte - Memory Cell: 1bit/Memory Cell
  • Highest performance
  • - Frequency : 104MHz - Internal ECC Implementation: 1-bit ECC - Read Performance - Read from Cell to Register with Internal ECC: 100us - Write Performance - Program time: 400us - typical - Block Erase time: 4ms
    • typical
  • Low Power with Wide Temp. Ranges
  • - Single 3.3V (2.7V to 3.6V) Voltage Supply - 10 mA Active Read Current - 8 µA Standby Current - Temp Grades: - Industrial: -40°C to +85°C - Extended: -40°C to +105°C (2) - Automotive, A1: -40°C to +85°C - Automotive, A2: -40°C to +105°C (2)

概觀

The serial electrical interface follows the industry-standard serial peripheral interface (SPI), providing a cost-effective non- volatile memory storage solution in systems where pin count must be kept to a minimum. The ISSI IS37/38SML01G1 is a 1Gb SLC SPI-NAND Flash memory device based on the standard parallel NAND Flash, but new command protocols and registers are defined for SPI operation. It is also an alternative to SPI-NOR, offering superior write performance and cost per bit over SPI-NOR. The command set resembles common SPI-NOR command set, modified to handle NAND-specific functions and new features. New features include user-selectable internal ECC. With internal ECC enabled, ECC code is generated internally when a page is written to memory array. The ECC code is stored in the spare area of each page. When a page is read to the cache register, the ECC code is calculated again and compared with the stored value. Errors are corrected if necessary. The device either outputs corrected data or returns an ECC error status. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The device contains 1024 blocks, composed by 64 pages consisting in two NAND structure of 32 series connected Flash cells. Each page consists 2112-Byte and is further divided into a 2048-Byte data storage area with a separate 64-Byte spare area. The 64-Byte area is typically used for memory and error management. The copy back function allows the optimization of defective blocks management: when a page program operation fails, the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. The pins serve as the ports for signals. The device has six signal lines plus Vcc and ground (GND, Vss). The signal lines are SCK (serial clock), SI (command and data input), SO (response and data output), and control signals CS#, HOLD#, WP#.