容量 1G
電壓 3.3V
Ecc要求 1-bit
總線寬度 X8
連續讀取速度(NS) 25
温規 -40°C to 105°C
腳位/封裝 48-TSOP, 63-BGA
狀態 Prod

IS35ML01G081-TLA1 特徵

  • Flexible & Efficient Memory Architecture
  • - Organization: 128Mb x8 - Memory Cell Array: (128M + 4M) x 8bit - Data Register: (2K + 64) x 8bit - Page Size: (2K + 64) Byte - Block Erase: (128K + 4K) Byte - Memory Cell: 1bit/Memory Cell
  • Highest performance
  • - Read Performance - Random Read: 25us (Max.) - Serial Access: 25ns (Max.) - Write Performance - Program time: 400us - typical - Block Erase time: 3ms
    • typical
  • Low Power with Wide Temp. Ranges
  • - Single 3.3V (2.7V to 3.6V) Voltage Supply - 15 mA Active Read Current - 10 µA Standby Current - Temp Grades: - Industrial: -40°C to +85°C - Automotive, A1: -40°C to +85°C
  • Reliable CMOS Floating Gate Technology
  • - ECC Requirement: X8 - 1bit/512Byte - Endurance: 100K Program/Erase cycles - Data Retention: 10 years
  • Efficient Read and Program modes
  • - Command/Address/Data Multiplexed I/O Interface - Command Register Operation - Automatic Page 0 Read at Power-Up Option - Boot from NAND support - Automatic Memory Download - NOP: 4 cycles - Cache Program Operation for High Performance Program - Cache Read Operation - Copy-Back Operation - EDO mode - OTO Operation - Bad-Block-Protect
  • Advanced Security Protection
  • - Hardware Data Protection - Program/Erase Lockout during Power Transitions

概觀

The IS34/35ML1G081 is a 128Mx8bit with spare 4Mx8bit capacity. The device is offered in 3.3V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The device contains 1,024 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected Flash cells. A program operation allows to write the 2,112-Byte page in typical 400us and an erase operation can be performed in typical 3ms on a 128K-Byte for X8 device block. Data in the page mode can be read out at 25ns cycle time per Byte. The I/O pins serve as the ports for address and command inputs as well as data input/output. The copy back function allows the optimization of defective blocks management: when a page program operation fails, the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. The cache program feature allows the data insertion in the cache register while the data register is copied into the Flash array. This pipelined program operation improves the program throughput when long files are written inside the memory. A cache read feature is also implemented. This feature allows to dramatically improving the read throughput when consecutive pages have to be streamed out. This device includes extra feature: Automatic Read at Power Up.