類型 HyperFlash™
電壓 1.7-1.95V
频率 166 Mhz
温規 -40 to 125 deg °C
腳位/封裝 24-Ball BGA (6x8mm)
狀態 Prod

IS26KS128S-DPBLE00 特徵

  • 3.0V I/O, 11 bus signals
    • Single ended clock
  • 1.8V I/O, 12 bus signals
    • Differential clock (CK, CK#)
  • Chip Select (CS#)
  • 8-bit data bus (DQ[7:0])
  • Read-Write Data Strobe (RWDS)
    • HyperFlash memories use RWDS only as a Read Data Strobe High Performance
  • Up to 333 MB/s sustained read throughput
  • Double-Data Rate (DDR)
    • two data transfers per clock
  • 166-MHz clock rate (333 MB/s) at 1.8V VCC
  • 100-MHz clock rate (200 MB/s) at 3.0V VCC
  • 96-ns initial random read access time
    • Initial random access read latency: 5 to 16 clock cycles
  • Sequential burst transactions
  • Configurable Burst Characteristics
    • Wrapped burst lengths:
    • 16 bytes (8 clocks)
    • 32 bytes (16 clocks)
    • 64 bytes (32 clocks)
    • Linear burst
    • Hybrid option — one wrapped burst followed by linear burst
    • Wrapped or linear burst type selected in each transaction
    • Configurable output drive strength
  • Low Power Modes
    • Active Clock Stop During Read: 12 mA, no wake-up required
    • Standby: 25 µA (typical), no wake-up required
    • Deep Power-Down: 8 µA (typical)
    • 300 µs wake-up required
  • INT# output to generate external interrupt
    • Busy to Ready Transition
  • RSTO# output to generate system level power-on reset
    • User configurable RSTO# Low period
  • 512-byte Program Buffer
    • Programming in 16-byte half-page multiples, up to a maximum of 512-bytes
  • Sector Erase
    • Uniform 256-kB sectors
    • Optional Eight 4-kB Parameter Sectors (32 kB total)
  • Advanced Sector Protection
    • Volatile and non-volatile protection methods for each sector
  • Separate 1024-byte one-time program array
  • Operating Temperature
    • Industrial (
    • 40°C to +85°C)
    • Industrial Plus (
    • 40°C to +105°C)
    • Extended (
    • 40°C to +125°C)
  • ISO/TS16949 and AEC Q100 Certified
  • Endurance
    • 100,000 cycle endurance for any sector (minimum)
  • Retention
    • 20 year data retention (typical)
  • Power-On Reset, Erase and Program Current

概觀

The ISSI HyperFlash™ family of products are high-speed CMOS, MirrorBit® NOR flash devices with the HyperBus™ low signal count DDR (Double Data Rate) interface, that achieves high speed read throughput. The DDR protocol transfers two data bytes per clock cycle on the data (DQ) signals. A read or write access for the HyperFlash consists of a series of 16-bit wide, one clock cycle data transfers at the internal HyperFlash core and two corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ signals.