IS46TR81280C-125JBLA2-TR
特徵
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Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V
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Low Voltage (L): VDD and VDDQ = 1.35V + 0.1V, -0.067V
- Backward compatible to 1.5V
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High speed data transfer rates with system
frequency up to 933 MHz
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8 internal banks for concurrent operation
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8n-bit pre-fetch architecture
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Programmable CAS Latency
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Programmable Additive Latency: 0, CL-1,CL-2
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Programmable CAS WRITE latency (CWL) based
on tCK
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Programmable Burst Length: 4 and 8
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Programmable Burst Sequence: Sequential or
Interleave
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BL switch on the fly
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Auto Self Refresh(ASR)
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Self Refresh Temperature(SRT)
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Refresh Interval:
7.8 µs (8192 cycles/64 ms) Tc= -40°C to 85°C
3.9 µs (8192 cycles/32 ms) Tc= 85°C to 105°C
1.95 µs (8192 cycles/16 ms) Tc= 105°C to 115°C
0.97 µs (8192 cycles/8 ms) Tc= 115°C to 125°C
OPTIONS
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Configuration:
128Mx8
64Mx16
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Package:
96-ball BGA (9mm x 13mm) for x16
78-ball BGA (8mm x 10.5mm) for x8
SPEED BIN
Speed Option
125J
107M
JEDEC Speed Grade
DDR3-1600J
DDR3-1866M
DECEMBER 2020
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Partial Array Self Refresh
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Asynchronous RESET pin
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TDQS (Termination Data Strobe) supported (x8
only)
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OCD (Off-Chip Driver Impedance Adjustment)
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Dynamic ODT (On-Die Termination)
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Driver strength : RZQ/7, RZQ/6 (RZQ = 240 )
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Write Leveling
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Up to 200 MHz in DLL off mode