IS43TR81280C-125JBLI-TR
特徵
-
Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V
-
Low Voltage (L): VDD and VDDQ = 1.35V + 0.1V, -0.067V
- Backward compatible to 1.5V
-
High speed data transfer rates with system
frequency up to 933 MHz
-
8 internal banks for concurrent operation
-
8n-bit pre-fetch architecture
-
Programmable CAS Latency
-
Programmable Additive Latency: 0, CL-1,CL-2
-
Programmable CAS WRITE latency (CWL) based
on tCK
-
Programmable Burst Length: 4 and 8
-
Programmable Burst Sequence: Sequential or
Interleave
-
BL switch on the fly
-
Auto Self Refresh(ASR)
-
Self Refresh Temperature(SRT)
-
Refresh Interval:
7.8 µs (8192 cycles/64 ms) Tc= -40°C to 85°C
3.9 µs (8192 cycles/32 ms) Tc= 85°C to 105°C
1.95 µs (8192 cycles/16 ms) Tc= 105°C to 115°C
0.97 µs (8192 cycles/8 ms) Tc= 115°C to 125°C
OPTIONS
-
Configuration:
128Mx8
64Mx16
-
Package:
96-ball BGA (9mm x 13mm) for x16
78-ball BGA (8mm x 10.5mm) for x8
SPEED BIN
Speed Option
125J
107M
JEDEC Speed Grade
DDR3-1600J
DDR3-1866M
DECEMBER 2020
-
Partial Array Self Refresh
-
Asynchronous RESET pin
-
TDQS (Termination Data Strobe) supported (x8
only)
-
OCD (Off-Chip Driver Impedance Adjustment)
-
Dynamic ODT (On-Die Termination)
-
Driver strength : RZQ/7, RZQ/6 (RZQ = 240 )
-
Write Leveling
-
Up to 200 MHz in DLL off mode