規格 128Mx8
類型 DDR2
電壓 1.8V
刷新 8K
速度 25 = up to 400 Mhz
腳位/封裝 BGA(60)
狀態 Prod
型號別 IBIS
產品系列 43 = 商業/工業級DDR/DDR2/DDR3/DDR4
總線寬度 8 = x8
字數 1280 = 128M
代/版本 C
CL(CAS延遲) D = 5
焊接 L = SnAgCu
温規 [空白] = 商規 (0C to +70°C)

IS43DR81280C-25DBL 特徵

  • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
  • JEDEC standard 1.8V I/O (SSTL_18-compatible)
  • Double data rate interface: two data transfers per clock cycle
  • Differential data strobe (DQS, DQS)
  • 4-bit prefetch architecture
  • On chip DLL to align DQ and DQS transitions with CK
  • 8 internal banks for concurrent operation
  • Programmable CAS latency (CL) 3, 4, 5, 6 and 7 supported
  • Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, 5 and 6 supported
  • WRITE latency = READ latency - 1 tCK
  • Programmable burst lengths: 4 or 8
  • Adjustable data-output drive strength, full and reduced strength options
  • On-die termination (ODT) OPTIONS
  • Configuration(s): 128Mx8 (16Mx8x8 banks): IS43/46DR81280C 64Mx16 (8Mx16x8 banks): IS43/46DR16640C
  • Package: x8: 60-ball BGA (8mm x 10.5mm) x16: 84-ball WBGA (8mm x 12.5mm)
  • Timing
    • Cycle time 2.5ns @CL=5 DDR2-800D 2.5ns @CL=6 DDR2-800E 3.0ns @CL=5 DDR2-667D 3.75ns @CL=4 DDR2-533C 5ns @CL=3 DDR2-400B

概觀

ISSI's 1Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.