IS43DR81280A-25EBL

規格	64Mx16
腳位/封裝	BGA(84)
電壓	1.8V
刷新	8K
速度	25 = 400MHz
字數	128M
型號別	IBIS
焊接	SnAgCu
狀態	OBS
類型	DDR2
總線寬度	8 = x8
温規	Commercial Grade (0C to +70°C)
CL（CAS延遲）	E = 6
代/版本	A
產品系列	43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
温度等级	blank = Commercial Grade (0°C to +70°C)
焊料類型	L = SnAgCu
字數	1280 = 128M
Generation	A = A
工作電壓範圍	DR = 1.8V DDR2
腳位/封裝	B = BGA

數據表

索取報價

IS43DR81280A-25EBL 特徵

Clock frequency up to 400MHz
8 internal banks for concurrent operation
4‐bit prefetch architecture
Programmable CAS Latency: 3, 4, 5, 6 and 7
Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6
Write Latency = Read Latency‐1
Programmable Burst Sequence: Sequential or Interleave
Programmable Burst Length: 4 and 8
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 7.8 s (8192 cycles/64 ms)
OCD (Off‐Chip Driver Impedance Adjustment)
ODT (On‐Die Termination)
Weak Strength Data‐Output Driver Option OPTIONS
Configuration:  128Mx8 (16M x 8 x 8 banks)  64Mx16 (8M x 16 x 8 banks)
Package:  60‐ball TW‐BGA for x8  84‐ball TW‐BGA for x16 SEPTEMBER 2011
Bidirectional differential Data Strobe (Single‐ ended data‐strobe is an optional feature)
On‐Chip DLL aligns DQ and DQs transitions with CK transitions
DQS# can be disabled for single‐ended data strobe
Read Data Strobe supported (x8 only)
Differential clock inputs CK and CK#
VDD and VDDQ = 1.8V ± 0.1V
PASR (Partial Array Self Refresh)
SSTL_18 interface
tRAS lockout supported

概觀

Input clocks Clock enable Chip Select Command control inputs Address Bank Address I/O Upper Byte Data Strobe Lower Byte Data Strobe Input data mask Supply voltage Ground DQ power supply DQ ground Reference voltage DLL power supply DLL ground On Die Termination Enable No connect.