IS43DR16320-37CBL

容量	512M
規格	32Mx16
電壓	1.8V
類型	DDR2
刷新	8K
速度	800, 667, 533
狀態	Contact ISSI
評注
腳位數	BGA(84)
產品系列	43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
字數	32037 = 32M
工作電壓範圍	DR = 1.8V DDR2
總線寬度	16 = x16

數據表

索取報價

IS43DR16320-37CBL 特徵

Clock frequency up to 400MHz
Posted CAS
Programmable CAS Latency: 3, 4, 5 and 6
Programmable Additive Latency: 0, 1, 2, 3, 4 and 5
Write Latency = Read Latency‐1
Programmable Burst Sequence: Sequential or Interleave
Programmable Burst Length: 4 and 8
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 7.8 μs (8192 cycles/64 ms)
OCD (Off‐Chip Driver Impedance Adjustment)
ODT (On‐Die Termination)
Weak Strength Data‐Output Driver Option
Bidirectional differential Data Strobe (Single‐ ended data‐strobe is an optional feature) OPTIONS
Configuration: − 64Mx8 (16M x 8 x 4 banks) − 32Mx16 (8M x 16 x 4 banks)
Package: − 60‐ball FBGA for x8 − 84‐ball FBGA for x16 Clock Cycle Timing ‐5B PRELIMINARY INFORMATION NOVEMBER 2009
On‐Chip DLL aligns DQ and DQs transitions with CK transitions
Differential clock inputs CK and CK#
VDD and VDDQ = 1.8V ± 0.1V
PASR (Partial Array Self Refresh)
SSTL_18 interface
Read Data Strobe supported (x8 only)
tRAS lockout supported Internal four bank operations with single pulsed RAS

概觀

Input clocks Clock enable Chip Select Command control inputs Address Bank Address I/O Upper Byte Data Strobe Lower Byte Data Strobe Input data mask Supply voltage Ground DQ power supply DQ ground Reference voltage DLL power supply DLL ground On Die Termination Enable No connect.

IC 編號

庫存數量

可用數量

IC 編號

庫存數量

可用數量

IS43DR16320-37CBL-TR

IS43DR16320-25EBLI-TR

IS43DR16320-25DBL

IS43DR16320-37CBLI

IS43DR16320-25DBL-TR

IS43DR16320-37CBLI-TR