IS43DR16160A-25EBLI

容量 256M
規格 16Mx16
電壓 1.8V
類型 DDR2
刷新 8K
速度 25 = 400MHz
狀態 EOL
評注
腳位數 WBGA(84)
温度等级 I = Industrial Grade (-40°C to +85°C)
焊料類型 L = SnAgCu
Generation A = A
字數 160 = 16M
CL(CAS延遲) E = 6
工作電壓範圍 DR = 1.8V DDR2
總線寬度 16 = x16
腳位/封裝 B = BGA
產品系列 43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade

IS43DR16160A-25EBLI 特徵

  • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
  • JEDEC standard 1.8V I/O (SSTL_18-compatible)
  • Double data rate interface: two data transfers per clock cycle
  • Differential data strobe (DQS, DQS)
  • 4-bit prefetch architecture
  • On chip DLL to align DQ and DQS transitions with CK
  • 4 internal banks for concurrent operation
  • Programmable CAS latency (CL) 3, 4, 5, and 6 supported
  • Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, and 5 supported
  • WRITE latency = READ latency - 1 tCK
  • Programmable burst lengths: 4 or 8
  • Adjustable data-output drive strength, full and reduced strength options
  • On-die termination (ODT) OPTIONS
  • Configuration(s): 32Mx8 (8Mx8x4 banks) IS43/46DR83200A 16Mx16 (4Mx16x4 banks) IS43/46DR16160A
  • Package: x8: 60-ball TW-BGA (8mm x 10.5mm) x16: 84-ball TW-BGA (8mm x 12.5mm) Timing
    • Cycle time 2.5ns @CL=6 DDR2-800E 3.0ns @CL=5 DDR2-667D 3.75ns @CL=4 DDR2-533C 5.0ns @CL=3 DDR2-400B

概觀

ISSI's 256Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.

 

相關IC编號

IC 編號 庫存數量 可用數量 IC 編號 庫存數量 可用數量
IS43DR16160A-25EBLI-TR 6,861 IS43DR16160A-3DBI-TR 6,171
IS43DR16160A-25EBL 6,192 IS43DR16160A-3DBL 30 6,364
IS43DR16160A-25EBL-TR 6,906 IS43DR16160A-3DBL-TR 6,495
IS43DR16160A-37CBL 21,822 4,831 IS43DR16160A-3DBLI 6,717
IS43DR16160A-37CBL-TR 6,143 IS43DR16160A-3DBLI-TR 6,927
IS43DR16160A-37CBLI 4,067 618 IS43DR16160A-5BBLI 15,329 6,270
IS43DR16160A-37CBLI-TR 6,328 IS43DR16160A-5BBLI-TR 6,734
IS43DR16160A-3DBI 6,347 3,854