1. 矽成
  2. 動態記憶體
  3. 第二代双倍数据率同步動態隨機存取記憶體
  4. 1.8V
  5. 2G 128Mx16
  6. BGA(84)
  7. IS43DR16128B-25EBL

  IS43DR16128B-25EBL

數據表
索取報價
容量 2G
規格 128Mx16
電壓 1.8V
類型 DDR2
刷新 8K
速度 25 = 400MHz
狀態 NR
評注
腳位數 BGA(84)
產品系列 43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
温度等级 blank = Commercial Grade (0°C to +70°C)
焊料類型 L = SnAgCu
字數 128 = 128M
CL（CAS延遲） E = 6
Generation B = B
工作電壓範圍 DR = 1.8V DDR2
總線寬度 16 = x16
腳位/封裝 B = BGA
數據表
索取報價

IS43DR16128B-25EBL 特徵

  • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
  • JEDEC standard 1.8V I/O (SSTL_18-compatible)
  • Double data rate interface: two data transfers per clock cycle
  • Differential data strobe (DQS, DQS)
  • 4-bit prefetch architecture
  • On chip DLL to align DQ and DQS transitions with CK
  • 8 internal banks for concurrent operation
  • Programmable CAS latency (CL) 3, 4, 5, 6, and 7 supported
  • Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, 5, and 6 supported
  • WRITE latency = READ latency - 1 tCK
  • Programmable burst lengths: 4 or 8
  • Adjustable data-output drive strength, full and reduced strength options
  • On-die termination (ODT) OPTIONS
  • Configuration(s): 256Mx8 (32Mx8x8 banks) IS43/46DR82560B 128Mx16 (16Mx16x8 banks) IS43/46DR16128B
  • Package: x8: 60-ball BGA (10.5mm x 13mm) x16: 84-ball WBGA (10.5mm x 13.5mm) Timing
    • Cycle time 2.5ns @CL=6 DDR2-800E 3.0ns @CL=5 DDR2-667D

概觀

ISSI's 2Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.

 

相關IC编號

IC 編號 庫存數量 可用數量 IC 編號 庫存數量 可用數量
IS43DR16128B-25EBL-TR 6,571 IS43DR16128B-3DBL 5,000
IS43DR16128B-25EBLI 5,026 IS43DR16128B-3DBL-TR 6,686
IS43DR16128B-25EBLI-TR 6,921 IS43DR16128B-3DBLI 5,000
IS43DR16128B-3DBI IS43DR16128B-3DBLI-TR 6,500
IS43DR16128B-3DBI-TR