1. 矽成
  2. 動態記憶體
  3. 第二代双倍数据率同步動態隨機存取記憶體
  4. 1.8V
  5. 2G 128Mx16
  6. BGA(84)
  7. IS43DR16128A-3DBLI-TR

  IS43DR16128A-3DBLI-TR

數據表
索取報價
容量 2G
規格 128Mx16
電壓 1.8V
類型 DDR2
刷新 8K
速度 3 = 333MHz
狀態 NR
評注
腳位數 BGA(84)
產品系列 43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
温度等级 I = Industrial Grade (-40°C to +85°C)
焊料類型 L = SnAgCu
字數 128 = 128M
CL（CAS延遲） D = 5
Generation A = A
工作電壓範圍 DR = 1.8V DDR2
總線寬度 16 = x16
腳位/封裝 B = BGA
外包裝 Tape on Reel
數據表
索取報價

IS43DR16128A-3DBLI-TR 特徵

  • Bidirectional differential Data Strobe (Single- ended data-strobe is an optional feature)
  • On-Chip DLL aligns DQ and DQs transitions with CK transitions
  • DQS# can be disabled for single-ended data strobe
  • Differential clock inputs CK and CK#
  • VDD and VDDQ = 1.8V ± 0.1V
  • PASR (Partial Array Self Refresh)
  • SSTL_18 interface tRAS lockout supported
  • Operating temperature: Commercial (TA = 0°C to 70°C ; TC = 0°C to 85°C) Industrial (TA = -40°C to 85°C; TC = -40°C to 95°C) Automotive, A1 (TA = -40°C to 85°C; TC = -40°C to 95°C) Automotive, A2 (TA = -40°C to 105°C; TC = -40°C to 105°C) ADDRESS TABLE Parameter Row Addressing Column Addressing Bank Addressing Precharge Addressing 128Mx16 A0-A13 A0-A9 BA0-BA2 A10 IS43/46DR16128A 2Gb (x16) DDR2 SDRAM
  • Clock frequency up to 333MHz
  • 8 internal banks for concurrent operation
  • 4-bit prefetch architecture
  • Programmable CAS Latency: 3, 4, 5, 6 and 7
  • Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6
  • Write Latency = Read Latency-1
  • Programmable Burst Sequence: Sequential or Interleave
  • Programmable Burst Length: 4 and 8
  • Automatic and Controlled Precharge Command
  • Power Down Mode
  • Auto Refresh and Self Refresh
  • Refresh Interval: 7.8 s (8192 cycles/64 ms)
  • ODT (On-Die Termination)
  • Weak Strength Data-Output Driver Option OPTIONS
  • Configuration:  128Mx16 (two-stacked 16M x 8 x 8 banks)

概觀

Power-up and Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power-up and Initialization Sequence The following sequence is required for Power-up and Initialization. 1. Either one of the following sequence is required for Power-up:

 

相關IC编號

IC 編號 庫存數量 可用數量 IC 編號 庫存數量 可用數量
IS43DR16128A-3DBLI 5,000 IS43DR16128A-3DBL 5,000
IS43DR16128A-3DBI IS43DR16128A-3DBL-TR 6,500
IS43DR16128A-3DBI-TR