IS46R16160F-5TLA1-TR

容量 256M
規格 16Mx16
電壓 2.5V
類型 DDR
刷新 8K
速度 5 = 200MHz
狀態 Prod
評注
腳位數 TSOP2(66), BGA(60)
温度等级 A1 = Automotive Grade (-40°C to +85°C)
焊料類型 L = 100% matte Sn
Generation F = F
字數 160 = 16M
工作電壓範圍 R = 2.5V DDR or 2.5V SDR
總線寬度 16 = x16
腳位/封裝 T = TSOP
產品系列 46 = DDR/DDR2/DDR3/DDR4 Automotive grade
外包裝 Tape on Reel

IS46R16160F-5TLA1-TR 特徵

  • VDD and VDDQ: 2.5V ± 0.2V
  • SSTL_2 compatible I/O
  • Double-data rate architecture; two data transfers per clock cycle
  • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver
  • DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs
  • Differential clock inputs (CK and CK)
  • DLL aligns DQ and DQS transitions with CK transitions
  • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
  • Four internal banks for concurrent operation
  • Data Mask for write data. DM masks write data at both rising and falling edges of data strobe
  • Burst Length: 2, 4 and 8
  • Burst Type: Sequential and Interleave mode
  • Programmable CAS latency: 2, 2.5 and 3
  • Auto Refresh and Self Refresh Modes
  • Auto Precharge
  • TRAS Lockout supported (tRAP = tRCD) OPTIONS
  • Configuration(s): 8Mx32, 16Mx16, 32Mx8
  • Package(s): 144 Ball BGA (x32) 66-pin TSOP-II (x8, x16) and 60 Ball BGA (x8, x16)
  • Lead-free package available

概觀

ISSI’s 256-Mbit DDR SDRAM achieves high speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 268,435,456-bit memory array is internally organized as four banks of 64Mb to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence and CAS latency enable further advantages. The device is available in 8-bit, 16-bit and 32-bit data word size Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CLK. Commands are registered on the positive edges of CLK. An Auto Refresh mode is provided, along with a Self Refresh mode. All I/Os are SSTL_2 compatible.

 

相關IC编號

IC 編號 庫存數量 可用數量 IC 編號 庫存數量 可用數量
IS46R16160F-5TLA1 6,892 IS46R16160F-6BLA2-TR 5,000
IS46R16160F-5BLA1 10 6,425 IS46R16160F-6TLA1 6,508
IS46R16160F-5BLA1-TR 7,500 IS46R16160F-6TLA1-TR 6,507
IS46R16160F-6BLA1 20 6,646 IS46R16160F-6TLA2 6,378
IS46R16160F-6BLA1-TR 7,500 IS46R16160F-6TLA2-TR 6,631
IS46R16160F-6BLA2 440 155