IS61NVP51218B-200B2I-TR

容量	9M
規格	512Kx18
電壓	2.5V
VccQ	2.5V
狀態	Prod
tKQ(ns)	2.6, 3.1
腳位數	BGA(119), QFP(100), BGA(165)
速度Mhz	250, 200
評論上一版本	P, IS61NVP51218A

數據表

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IS61NVP51218B-200B2I-TR 特徵

100 percent bus utilization
No wait cycles between Read and Write
Internal self-timed write cycle
Individual Byte Write Control
Single R/W (Read/Write) control pin
Clock controlled, registered address, data and control
Interleaved or linear burst sequence control us- ing MODE input
Three chip enables for simple depth expansion and address pipelining
Power Down mode
Common data inputs and data outputs
CKE pin to enable clock and suspend operation
JEDEC 100-pin QFP, 165-ball BGA and 119-ball BGA packages
Power supply: NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NVVP: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)
JTAG Boundary Scan for BGA packages
Industrial temperature available

概觀

, 100 percent bus utilization , No wait cycles between Read and Write , Internal self-timed write cycle , Individual Byte Write Control , Single R/W (Read/Write) control pin , Clock controlled, registered address,

IC 編號

庫存數量

可用數量

IC 編號

庫存數量

可用數量

IS61NVP51218B-200B2I

IS61NVP51218B-250B2I-TR

IS61NVP51218B-200B3I

IS61NVP51218B-250B3I

IS61NVP51218B-200B3I-TR

IS61NVP51218B-250B3I-TR