IS61NVF51236-7-TR - 日耀电子 | ISSI/蕊成授权代理

規格	512Kx36
腳位/封裝	QFP(100), BGA(165, 209)
tKQ	6.5, 7.5
電壓	2.5V
VccQ	2.5V
型號別	IBIS, BSDL
狀態	Prod
評注	F
外包裝	Tape on reel
速度（MHz）	133, 117

數據表

索取報價

IS61NVF51236-7-TR 特徵

100 percent bus utilization
No wait cycles between Read and Write
Internal self-timed write cycle
Individual Byte Write Control
Single Read/Write control pin
Clock controlled, registered address, data and control
Interleaved or linear burst sequence control us- ing MODE input
Three chip enables for simple depth expansion and address pipelining
Power Down mode
Common data inputs and data outputs
CKE pin to enable clock and suspend operation
JEDEC 100-pin TQFP, 165-ball PBGA and 209- ball (x72) PBGA packages
Power supply: NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
JTAG Boundary Scan for PBGA packages
Industrial temperature available

概觀

, 100 percent bus utilization , No wait cycles between Read and Write , Internal self-timed write cycle , Individual Byte Write Control , Single Read/Write control pin , Clock controlled, registered address,