IS66WVQ2M4EDBLL-133BLI-TR

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容量	8M
電壓	2.7-3.6V
狀態	S=NOW
I / O寬度	x4
腳位數	SOIC(16), BGA(24)
溫度範圍	-40 to 105°C
速度Mhz Ns	133 MHz
評論上一篇	Serial QUADRAM, ECC Based
包裝代碼	B = 24-ball TFBGA 6x8mm 5x5 ball array
Item	66 = Pseudo SRAM/HyperRAM™
ROHS版	L = true
產品類別	WVQ = QuadRAM
Revision	D = D
溫度範圍	I = Industrial (-40°C to 85°C)
速度	133 = 133 MHz
電壓 - 電源	BLL = 3V
密度配置	2M4 = 8Mb /2M x4
外包裝	Tape on Reel

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IS66WVQ2M4EDBLL-133BLI-TR 特徵

Hardware Features
- SCLK Input: Serial clock input - SIO0
- SIO3: Serial Data Input or Serial Data Output - DQSM: - Output during command, address transactions as Refresh Collision Indicator - Output during read data transactions as Read Data Strobe - Input during write data transactions as Write Data Mask - RESET#: Hardware Reset pin
Temperature Grades
- - Auto (A2) Grade: -40°C to +105°C Industrial: -40°C to +85°C
Industry Standard PACKAGE
- B = 24-ball TFBGA 6x8mm 5x5 Array - M = 16-pin 300mil SOIC(1) - KGD (Call Factory) Note: 1. 133MHz (max.) for 16-pin SOIC package
Industry Standard Serial Interface
- Quad DDR (x4 xSPI) Interface: Command (1 byte) =SDR Address (2-byte) & Data = DDR - Low Signal Counts :7 Signal pins (CS#, SCLK, DQSM, SIO0~SIO3)
High Performance
- On chip ECC (chunk size = 4 bit): 1-bit correction and 2-bit detection - Double Data Rate (DDR) Operation: 200MHz (200MB/s) at 1.8V VCC (1) 133MHz (133MB/s) at 3.0V VCC - Source Synchronous Output signal during Read Operation (DQSM) - Data Mask during Write Operation (DQSM) - Configurable Latency for Read/Write Operation - Supports Variable Latency mode and Fixed Latency mode - Configurable Drive Strength - Supports Wrapped Burst mode and Continuous mode - Supports Deep Power Down mode - Hidden Refresh
Burst Operation
- Configurable Wrapped Burst Length : 16, 32, 64, and 128 - Continuous Operation: - Continues Read operation until the end of array address (No Wrapped) - Continues Write operation even after the end of array address (Wrapped to first address)

概觀

The IS66/67WVQ2M4EDALL/BLL are integrated memory device containing 8Mb Pseudo Static Random Access Memory, using a self-refresh DRAM array organized as 1M words by 8 bits. The device supports Quad DDR interface, which is compatible with JEDEC standard x4 xSPI Flash. The device supports Very Low Signal Count (7 signal pins; SCLK, CS#, DQSM, and 4 SIOs) + optional ERR, Hidden Refresh Operation, and Automotive temperature (A2, -40°C to +105°C) operation. Due to DDR operation, minimum transferred data size is a byte (8 bits) through 4 SIO pins. PERFORMANCE SUMMARY.

IC 編號	庫存數量	可用數量	IC 編號	庫存數量	可用數量
IS66WVQ2M4EDBLL-133BLI			IS66WVQ2M4EDBLL-100MLI-TR
IS66WVQ2M4EDBLL-100BLI			IS66WVQ2M4EDBLL-133MLI
IS66WVQ2M4EDBLL-100BLI-TR			IS66WVQ2M4EDBLL-133MLI-TR
IS66WVQ2M4EDBLL-100MLI

IS66WVQ2M4EDBLL-133BLI-TR 特徵

概觀

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