IS61QDPB41M36A2-400M3L

容量 36M
規格 1Mx36
4
狀態 Prod
速度Mhz 300, 333, 400, 450
評論上一版本 2.5 Cycle Read Latency
配置 1M36 = 1M x36
ROHS版 L = Lead-free
突發類型 B4 = Burst 4
硅片版本 A = A
讀延時(RL) blank = 1.5 clock cycles or 2.5 clock cycles
產品類別 QDP = QUADP
ODT選項 2 = ODT Option 2 If ODT = HIGH, a high range termination resistance is selected. If ODT = LOW or floating, ODT is disabled
溫度範圍 blank = Commercial (0°C to 70°C)
速度 400 = 400MHz
產品系列 61 = QUAD/P DDR-2/P
包裝代碼 M3 = 165-ball BGA (15 x 17 mm)

IS61QDPB41M36A2-400M3L 特徵

  • 1Mx36 and 2Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with late write operation.
  • Double Data Rate (DDR) interface for read and write input ports. 2.5 cycle read latency. Fixed 4-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
  • Read/write address
  • Read enable
  • Write enable
  • Byte writes for burst addresses 1 and 3
  • Data-in for burst addresses 1 and 3
  • HSTL input and output levels.
  • Registered addresses, write and read controls, byte writes, data in, and data outputs.
  • Full data coherency.
  • Boundary scan using limited set of JTAG 1149.1 functions.
  • Byte write capability.
  • Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
  • Programmable impedance output drivers via 5x user-supplied precision resistor.
  • ODT (On Die Termination) feature is supported
  • optionally on data input, K/K#, and BWx#. The end of top mark (A/A1/A2) is to define options. IS61QDPB41M36A : Don’t care ODT function and pin connection IS61QDPB41M36A1 : Option1 IS61QDPB41M36A2 : Option2 Refer to more detail description at page 6 for each ODT option. The following are registered on the rising edge of the K# clock:
  • Byte writes for burst addresses 2 and 4

概觀

The 36Mb IS61QDPB41M36A/A1/A2 and IS61QDPB42M18A/A1/A2 are synchronous, high- performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUADP (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock:

 

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IS61QDPB41M36A1-300B4I-TR IS61QDPB41M36A2-300M3L
IS61QDPB41M36A1-300B4L IS61QDPB41M36A2-300M3L-TR
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