1. 矽成
  2. 靜態隨機存取存儲器
  3. QUAD/QUADP and DDR-II/DDR-IIP
  4. QUADP
  5. 72M 2Mx36
  6. 165 ball BGA (13 x 15 mm)
  7. IS61QDP2B42M36A-333B4L-TR

  IS61QDP2B42M36A-333B4L-TR

數據表
索取報價
容量 72M
規格 2Mx36
陣 4
狀態 Prod
速度Mhz 300, 333, 400, 450
評論上一版本 2.0 Cycle Read Latency
產品系列 61 = QUAD/P DDR-2/P
配置 2M36 = 2M x36
包裝代碼 B4 = 165 ball BGA (13 x 15 mm)
ROHS版 L = Lead-free
突發類型 B4 = Burst 4
硅片版本 A = A
讀延時（RL） 2 = 2.0 clock cycles
ODT選項 blank = No ODT
產品類別 QDP = QUADP
溫度範圍 blank = Commercial (0°C to 70°C)
速度 333 = 333MHz
外包裝 Tape on Reel
數據表
索取報價

IS61QDP2B42M36A-333B4L-TR 特徵

  • 2Mx36 and 4Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with late write operation.
  • Double Data Rate (DDR) interface for read and write input ports. 2.0 cycle read latency. Fixed 4-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
  • Data Valid Pin (QVLD).
  • HSTL input and output interface.
  • Registered addresses, write and read controls, byte writes, data in, and data outputs.
  • Full data coherency.
  • Boundary scan using limited set of JTAG 1149.1 functions.
  • Byte write capability.
  • Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
  • Programmable impedance output drivers via 5x user-supplied precision resistor.
  • ODT (On Die Termination) feature is supported
  • Read/write address
  • Read enable
  • Write enable
  • Byte writes for burst addresses 1 and 3
  • Data-in for burst addresses 1 and 3 The following are registered on the rising edge of the K# clock:
  • Byte writes for burst addresses 2 and 4

概觀

The 72Mb IS61QDP2B42M36A/A1/A2 and IS61QDP2B42M36A/A1/A2 are synchronous, high- performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUADP (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock:

 

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IS61QDP2B42M36A-300M3-TR IS61QDP2B42M36A1-333M3L
IS61QDP2B42M36A-300M3L 10,000 IS61QDP2B42M36A1-333M3L-TR
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IS61QDP2B42M36A-333B4-TR IS61QDP2B42M36A2-300B4-TR
IS61QDP2B42M36A-333M3 IS61QDP2B42M36A2-300B4L
IS61QDP2B42M36A-333M3-TR IS61QDP2B42M36A2-300B4L-TR
IS61QDP2B42M36A-333M3L 10,000 IS61QDP2B42M36A2-300M3
IS61QDP2B42M36A-333M3L-TR IS61QDP2B42M36A2-300M3-TR
IS61QDP2B42M36A-400B4 IS61QDP2B42M36A2-300M3L
IS61QDP2B42M36A-400B4-TR IS61QDP2B42M36A2-300M3L-TR
IS61QDP2B42M36A1-300B4 IS61QDP2B42M36A2-333B4
IS61QDP2B42M36A1-300B4-TR IS61QDP2B42M36A2-333B4-TR
IS61QDP2B42M36A1-300B4L IS61QDP2B42M36A2-333B4L
IS61QDP2B42M36A1-300B4L-TR IS61QDP2B42M36A2-333B4L-TR
IS61QDP2B42M36A1-300M3 IS61QDP2B42M36A2-333M3
IS61QDP2B42M36A1-300M3-TR IS61QDP2B42M36A2-333M3-TR
IS61QDP2B42M36A1-300M3L IS61QDP2B42M36A2-333M3L
IS61QDP2B42M36A1-300M3L-TR IS61QDP2B42M36A2-333M3L-TR
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