| 容量 | 72M |
|---|---|
| 規格 | 4Mx18 |
| 陣 | 4 |
| 型號別 | ibis/verilog |
| 狀態 | Prod |
| 評注 | 2.5 Cycle Read, Application Note |
| 速度（MHz） | 300, 333, 400, 450 |
| 產品系列 | 61 = QUAD/P DDR-2/P |
| 配置 | 4M18 = 4M x18 |
| 突發類型 | B4 = Burst 4 |
| 硅片版本 | A = A |
| 讀延時（RL） | blank = 1.5 clock cycles or 2.5 clock cycles |
| ODT選項 | 2 = ODT Option 2 If ODT = HIGH, a high range termination resistance is selected. If ODT = LOW or floating, ODT is disabled |
| 產品類別 | DDP = DDR-IIP, Common I/O |