| 規格 | 4Mx18 |
|---|---|
| 腳位/封裝 | 165 ball BGA (13 x 15 mm) |
| 陣 | 2 |
| 型號別 | ibis/verilog |
| 焊接 | Leaded |
| 狀態 | Prod |
| 評注 | 2.5 Cycle Read |
| 速度（MHz） | 500 |
| 温規 | Industrial Grade (-40C to +85°C) |
| 產品類別 | DDP = DDR-IIP, Common I/O |
| 讀延時（RL） | blank = 1.5 clock cycles or 2.5 clock cycles |
| 產品系列 | 61 = QUAD/P DDR-2/P |
| 配置 | 2M36 = 2M x36 |
| 包裝代碼 | B4 = 165 ball BGA (13 x 15 mm) |
| ROHS版 | = Leaded |
| 突發類型 | B2 = Burst 2 |
| 硅片版本 | B = B |
| ODT選項 | 2 = ODT Option 2 If ODT = HIGH, a high range termination resistance is selected. If ODT = LOW or floating, ODT is disabled |
| 溫度範圍 | I = Industrial (-40°C to +85°C) |
| 速度 | 500 = 500MHz |