1. 矽成
  2. Mobile DRAM
  3. LPDDR4/LPDDR4X SDRAM
  4. LPDDR4X with ECC SDRAM
  5. 0.6V/1.1V/1.8V
  6. 4G Two channel (2x16)
  7. BGA(200)
  8. IS43LQ32128EAL-062B2LI

  IS43LQ32128EAL-062B2LI

數據表
索取報價
Buy
容量 4G
規格 Two channel (2x16)
電壓 0.6V/1.1V/1.8V
類型 LPDDR4X
速度 3200
狀態 Prod
腳位數 BGA(200)
產品系列 43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
温度等级 blank = Commercial Grade (0°C to +70°C)
焊料類型 blank = Sn/Pb
字數 128 = 128M
Low Voltage L = Supports only 0.6V I/O (LPDDR4X)
Generation EA = EA
工作電壓範圍 LQ = 1.1V LPDDR4
總線寬度 32 = x32
腳位/封裝 B = BGA
數據表
索取報價

IS43LQ32128EAL-062B2LI 特徵

  • On-chip temperature sensor whose status can be read from MR4
  • 200-ball x16/x32 BGA (10x14.5mm) ADDRESS TABLE * Parameter # of Channel Row Addresses Column Addresses Bank Addresses Note: Address information is per channel base. R0-R14 1 C0-C9 BA0-BA2 2 R0-R13 Speed Grade KEY TIMING PARAMETERS Write Latency Set B 26 22 Set A 14 12 Data Rate (Mb/s) Freq. (MHz) 3200 2666
  • -062 -075 1600 1333 Read Latency DBI DBI OFF ON 32 28 24 28 Configuration: - 256Mb x16 x 1 channel - 128Mb x 16 x 2 channels - 8 internal banks per channel
  • On-Chip ECC:
  • - Single-bit error correction (per 64-bits)
  • Low-voltage Core and I/O Power Supplies VDD1 = 1.70-1.95V VDD2 = 1.06-1.17V VDDQ = 1.06-1.17V (LPDDR4) VDDQ = 0.57-0.65V (LPDDR4X) LVSTL(Low Voltage Swing Terminated Logic) I/O Interface Internal VREF and VREF Training
  • Dynamic ODT : DQ ODT :VSSQ Termination CA ODT :VSS Termination
  • Max. Clock Frequency : 1.6GHz (3.2Gbps)
  • 16n Pre-fetch DDR architecture
  • Single data rate (multiple cycles) command/ address bus
  • Bidirectional/differential data strobe per byte of data (DQS/DQS#)
  • Programmable burst lengths (16 or 32)
  • ZQ Calibration
  • Operation Temperature Industrial (TC = -40°C to 95°C) Automotive, A1 (TC = -40°C to 95°C) Automotive, A2 (TC = -40°C to 105°C) Automotive, A3 (TC = -40°C to 125°C)

概觀

The IS43/46LQ16256EA/EAL and IS43/46LQ32128EA/EAL are 4Gbit CMOS LPDDR4 SDRAM. The device is organized as 1/2 channels per device, and individual channel is 8-banks and 16-bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 16N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth. , On-chip temperature sensor whose status.

 

相關IC编號

IC 編號 庫存數量 可用數量 IC 編號 庫存數量 可用數量
IS43LQ32128EAL-062B2LI-TR IS43LQ32128EAL-075B2LI-TR
IS43LQ32128EAL-062BLI IS43LQ32128EAL-075BLI
IS43LQ32128EAL-062BLI-TR IS43LQ32128EAL-075BLI-TR
IS43LQ32128EAL-075B2LI