IS46DR16128-3DBLA2 - 日耀电子 | ISSI/蕊成授权代理

容量	2G
規格	128Mx16
腳位/封裝	BGA(84)
電壓	1.8V
刷新	8K
速度	up to 333 Mhz
字數	128M
型號別	IBIS
焊接	SnAgCu
狀態	EOL
類型	DDR2
總線寬度	16 = x16
温規	Automotive Grade (-40C to +105°C)
CL（CAS延遲）	5
產品系列	46 = DDR/DDR2/DDR3/DDR4 Automotive grade
字數	1283 = 1283M
工作電壓範圍	DR = 1.8V DDR2

數據表

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IS46DR16128-3DBLA2 特徵

Clock frequency up to 333MHz (667 MT/s Data Rate)
8 internal banks for concurrent operation
4-bit prefetch architecture
Programmable CAS Latency: 3, 4, 5, 6 and 7
Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6
Write Latency = Read Latency-1
Programmable Burst Sequence: Sequential or Interleave
Programmable Burst Length: 4 and 8
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 7.8 µs (8192 cycles/64 ms)
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
Weak Strength Data-Output Driver Option OPTIONS
Configuration: − 128Mx16 (two stacked 16M x 8 x8 banks)
Package: − 84-ball FBGA Clock Cycle Timing SEPTEMBER 2012
Bidirectional differential Data Strobe (Single-ended data-strobe is an optional feature)
On-Chip DLL aligns DQ and DQs transitions with CK transitions
DQS# can be disabled for single-ended data strobe
Differential clock inputs CK and CK#
VDD and VDDQ = 1.8V ± 0.1V
PASR (Partial Array Self Refresh)
SSTL_18 interface
tRAS lockout supported

概觀

Input clocks Clock enable Chip Select Command control inputs Address Bank Address I/O Upper Byte Data Strobe Lower Byte Data Strobe Input data mask Supply voltage Ground DQ power supply DQ ground Reference voltage DLL power supply DLL ground On Die Termination Enable No connect.