IS43DR32800A-5BBL-TR

規格	8Mx32
腳位/封裝	BGA(126)
電壓	1.8V
刷新	4K
速度	5 = 200MHz
字數	8M
型號別	IBIS
焊接	SnAgCu
狀態	OBS
外包裝	Tape on Reel
類型	DDR2
總線寬度	32 = x32
温規	Commercial Grade (0C to +70°C)
CL（CAS延遲）	B = 3
代/版本	A
產品系列	43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
温度等级	blank = Commercial Grade (0°C to +70°C)
焊料類型	L = SnAgCu
字數	800 = 8M
Generation	A = A
工作電壓範圍	DR = 1.8V DDR2
腳位/封裝	B = BGA

數據表

索取報價

IS43DR32800A-5BBL-TR 特徵

Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS)
4-bit prefetch architecture
On chip DLL to align DQ and DQS transitions with CK
4 internal banks for concurrent operation
Programmable CAS latency (CL) 3, 4, 5, and 6 supported
Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, and 5 supported
WRITE latency = READ latency - 1 tCK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength, full and reduced strength options
On-die termination (ODT) OPTIONS
Configuration: 8M x 32 (IS43DR32800A Standard Page - 4K refresh) 8M x 32 (IS43/46DR32801A Reduced Page - 8K refresh)
Package: x32: 126 WBGA
Timing
- Cycle time 3.0ns @CL=5, DDR2-667D 3.75ns @CL=4, DDR2-533C 5.0ns @CL=3, DDR2-400B

概觀

ISSI's 256Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. The 256Mb DDR2 SDRAM is provided in a wide bus x32 format, designed to offer a smaller footprint and support compact designs.