概觀
ISSI’s 512-Mbit DDR SDRAM achieves high speed data
transfer using pipeline architecture and two data word
accesses per clock cycle. The 536,870,912-bit memory
array is internally organized as four banks of 128Mb to
allow concurrent operations. The pipeline allows Read
and Write burst accesses to be virtually continuous, with
the option to concatenate or truncate the bursts. The
programmable features of burst length, burst sequence
and CAS latency enable further advantages. The device
is available in 8-bit and 16-bit word size. Input data is
registered on the I/O pins on both edges of Data Strobe
signal(s), while output data is referenced to both edges
of Data Strobe and both edges of CLK. Commands are
registered on the positive edges of CLK.
An Auto Refresh mode is provided, along with a Self
Refresh mode. All I/Os are SSTL_2 compatible.