| 容量 | 2M |
|---|---|
| 規格 | 128Kx16 |
| 電壓 | 1.65-3.6V |
| 狀態 | Prod |
| 腳位數 | TSOP2(44), BGA(48) |
| 速度Ns | 8, 10, 12 |
| 評論上一篇 | ECC Based SRAM |
SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM has three different modes supported. Each function is described below with Truth Table. STANDBY MODE Device enters standby mode when deselected (CS# HIGH). The input and output pins (I/O0-15) are placed in a high impedance state. CMOS input in this mode will maximize saving power. WRITE MODE Write operation issues with Chip selected (CS#) and Write Enable (WE#) input LOW. The input and output pins (I/O0- 15) are in data input mode. Output buffers are closed during this time even if OE# is LOW. UB# and LB# enables a byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the location specified on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written into the location. READ MODE Read operation issues with Chip selected (CS# LOW) and Write Enable (WE#) input HIGH. When OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB# and LB# enables a byte read feature. By enabling LB# LOW, data from memory appears on I/O0-7. And with UB# being LOW, data from memory appears on I/O8-15. In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used. ERROR DETECTION AND ERROR CORRECTION.