IS61NVVP204818B-166B3-TR

Density 36M
Org 2Mx18
Vcc 1.8V
VccQ 1.8V
Status Prod
tKQ(ns) 2.6, 3.1, 3.5
Pkg Pins QFP(100), BGA(165, 119)
Speed Mhz 250, 200, 166
Comment Prev Rev P

IS61NVVP204818B-166B3-TR Features

  • 100 percent bus utilization
  • No wait cycles between Read and Write
  • Single R/W (Read/Write) control pin
  • Clock controlled, registered address, Internal self-timed write cycle Individual Byte Write Control
  • data and control Interleaved or linear burst sequence control us- ing MODE input
  • Three chip enables for simple depth expansion and address pipelining
  • Power Down mode
  • Common data inputs and data outputs
  • CKE pin to enable clock and suspend operation
  • JEDEC 100-pin TQFP, 165-ball PBGA and 119- ball PBGA packages
  • Power supply: NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NVVP: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)
  • JTAG Boundary Scan for PBGA packages

Overview

, 100 percent bus utilization , No wait cycles between Read and Write , , , Single R/W (Read/Write) control pin , Clock controlled, registered address,

 

Related Part Number(s)

Description Stock Qty Available Qty Description Stock Qty Available Qty
IS61NVVP204818B-166B3 IS61NVVP204818B-166B3L-TR
IS61NVVP204818B-166B2 IS61NVVP204818B-166B3LI
IS61NVVP204818B-166B2-TR IS61NVVP204818B-166B3LI-TR
IS61NVVP204818B-166B2I IS61NVVP204818B-166TQ
IS61NVVP204818B-166B2I-TR IS61NVVP204818B-166TQ-TR
IS61NVVP204818B-166B2L IS61NVVP204818B-166TQI
IS61NVVP204818B-166B2L-TR IS61NVVP204818B-166TQI-TR
IS61NVVP204818B-166B2LI IS61NVVP204818B-166TQL
IS61NVVP204818B-166B2LI-TR IS61NVVP204818B-166TQL-TR
IS61NVVP204818B-166B3I IS61NVVP204818B-166TQLI
IS61NVVP204818B-166B3I-TR IS61NVVP204818B-166TQLI-TR
IS61NVVP204818B-166B3L