IS61NVVP204818B-166B2L-TR

Density	36M
Org	2Mx18
Vcc	1.8V
VccQ	1.8V
Status	Prod
tKQ(ns)	2.6, 3.1, 3.5
Pkg Pins	QFP(100), BGA(165, 119)
Speed Mhz	250, 200, 166
Comment Prev Rev	P

Datasheet

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IS61NVVP204818B-166B2L-TR Features

100 percent bus utilization
No wait cycles between Read and Write
Single R/W (Read/Write) control pin
Clock controlled, registered address, Internal self-timed write cycle Individual Byte Write Control
data and control Interleaved or linear burst sequence control us- ing MODE input
Three chip enables for simple depth expansion and address pipelining
Power Down mode
Common data inputs and data outputs
CKE pin to enable clock and suspend operation
JEDEC 100-pin TQFP, 165-ball PBGA and 119- ball PBGA packages
Power supply: NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NVVP: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)
JTAG Boundary Scan for PBGA packages

Overview

, 100 percent bus utilization , No wait cycles between Read and Write , , , Single R/W (Read/Write) control pin , Clock controlled, registered address,

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IS61NVVP204818B-166B2L

IS61NVVP204818B-166B3L-TR

IS61NVVP204818B-166B2

IS61NVVP204818B-166B3LI

IS61NVVP204818B-166B2-TR

IS61NVVP204818B-166B3LI-TR