IS43LR16128B-5BLI
Features
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JEDEC standard 1.8V power supply.
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64ms refresh period (8K cycle)
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VDD = 1.8V, VDDQ = 1.8V
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Auto & self refresh
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Four internal banks for concurrent operation
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Concurrent Auto Precharge
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MRS cycle with address key programs
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Maximum clock frequency up to 208MHZ
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- CAS latency 2, 3 (clock)
- Burst length (2, 4, 8, 16)
- Burst type (sequential & interleave)
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Fully differential clock inputs (CK, /CK)
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Maximum data rate up to 416Mbps/pin
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Power Saving support
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- PASR (Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
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All inputs except data & DM are sampled at the rising
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- Deep Power Down Mode
edge of the system clock
- Programmable Driver Strength Control by Full Strength
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Data I/O transaction on both edges of data strobe
or 1/2, 1/4, 1/8 or 3/4 of Full Strength
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Bidirectional data strobe per byte of data (DQS)
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Status Register Read (SRR)
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DM for write masking only
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LVCMOS compatible inputs/outputs
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Edge aligned data & data strobe output
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Operation Temperature:
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- Commercial (TA= 0 ~ 70 C )
- Industrial (TA= -40 ~ 85 C )
- Automotive, A1 (TA= -40 ~ 85 C )
- Automotive, A2 (TA= -40 ~ 105 C )
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Center aligned data & data strobe input
OPTIONS
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Configuration:
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- 128Mx16 (32M x16 x 4 banks)
- 64Mx32 (16M x32 x 4 banks)