規格 4Mx32
類型 SDR
電壓 3.3V
刷新 4K
速度 7 = up to 143Mhz
腳位/封裝 T = TSOP
狀態 S=Q3/17
產品系列 45 = 車規SDRAM
總線寬度 32 = x32
字數 400 = 4M
代/版本 J
焊接 L = 100% matte Sn
温規 A1 = 車規 (-40C to +85°C)
外包裝 卷轴包

IS45S32400J-7TLA1-TR 特徵

  • Clock frequency: 166, 143, 133 MHz
  • Fully synchronous; all signals referenced to a positive clock edge
  • Internal bank for hiding row access/precharge
  • Single Power supply: 3.3V + 0.3V
  • LVTTL interface
  • Programmable burst length
    • (1, 2, 4, 8, full page)
  • Programmable burst sequence: Sequential/Interleave
  • Auto Refresh (CBR)
  • Self Refresh
  • 4096 refresh cycles every 16ms (A2 grade) or 64 ms (Commercial, Industrial, A1 grade)
  • Random column address every clock cycle
  • Programmable CAS latency (2, 3 clocks)
  • Burst read/write and burst read/single write operations capability
  • Burst termination by burst stop and precharge command OPTIONS
  • Package: 86-pin TSOP-II 90-ball TF-BGA

概觀

ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks.