IS49NLS96400A-33BLI

規格 32Mx18
腳位/封裝 BGA(144)
速度 tCK = 3.3ns; tRC = 20ns
焊接 Lead-free (RoHS Compliant)
狀態 Prod
接口 Separate I/O
温規 Industrial Grade (-40C to +85°C)
產品系列 49NL = RLDRAM 2
配置 96400 = 64M x 9
Generation A = A
ROHS版 L = Lead-free (RoHS compliant)
Package Number B = 144-ball FBGA (RLDRAM 2)
I / O類型 S = Separate I/O
溫度範圍 I = Industrial (-40C to 85°C)
包裝代碼 B = B
速度等級 33 = tCK = 3.3ns; tRC = 20ns

IS49NLS96400A-33BLI 特徵

  • Differential input clocks (CK, CK#)
  • Differential input data clocks (DKx, DKx#)
  • On-die DLL generates CK edge-aligned data and output data clock signals
  • Data valid signal (QVLD)
  • HSTL I/O (1.5V or 1.8V nominal)
  • 25-60Ω matched impedance outputs
  • 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
  • On-die termination (ODT) RTT
  • Operating temperature: IEEE 1149.1 compliant JTAG boundary scan Commercial (TC = 0° to +95°C) Industrial (TC = -40°C to +95°C; TA = -40°C to +85°C) 576Mb (64Mbx9, 32Mbx18) Seperate I/O RLDRAM 2 Memory
  • 533MHz DDR operation (1.067 Gb/s/pin data rate) 38.4Gb/s peak bandwidth (x18 at 533 MHz clock frequency)
  • Reduced cycle time (15ns at 533MHz)
  • 32ms refresh (16K refresh for each bank; 128K refresh command must be issued in total each 32ms)
  • 8 internal banks
  • Non-multiplexed addresses (address multiplexing option available)
  • SRAM-type interface
  • Programmable READ latency (RL), row cycle time, and burst sequence length
  • Balanced READ and WRITE latencies in order to optimize data bus utilization
  • Data mask signals (DM) to mask signal of WRITE data; DM is sampled on both edges of DK. OPTIONS
  • Package:  144-ball FBGA (leaded)  144-ball FBGA (lead-free)  144-ball WBGA (lead-free)
  • Configuration:  64Mx9  32Mx18