容量 128M
規格 8Mx16
類型 MDDR
電壓 1.8V
刷新 4K
速度(MHz) 166
腳位/封裝 BGA(60)
狀態 EOL
型號別 IBIS
產品系列 46 = 車規DDR/DDR2/DDR3/DDR4
總線寬度 16 = x16
字數 800 = 8M
代/版本 F
焊接 L = SnAgCu
温規 A2 = 車規 (-40C to +105°C)

IS46LR16800F-6BLA2 特徵

  • JEDEC standard 1.8V power supply.
  • VDD = 1.8V, VDDQ = 1.8V
  • Four internal banks for concurrent operation
  • MRS cycle with address key programs
  • - CAS latency 2, 3 (clock) - Burst length (2, 4, 8, 16) - Burst type (sequential & interleave)
  • Fully differential clock inputs (CK, /CK)
  • All inputs except data & DM are sampled at the rising edge of the system clock
  • Data I/O transaction on both edges of data strobe
  • Bidirectional data strobe per byte of data (DQS)
  • DM for write masking only
  • Edge aligned data & data strobe output
  • Center aligned data & data strobe input
  • 64ms refresh period (4K cycle)
  • Auto & self refresh
  • Concurrent Auto Precharge
  • Maximum clock frequency up to 166MHZ
  • Maximum data rate up to 333Mbps/pin
  • Power Saving support - PASR (Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - Deep Power Down Mode - Programmable Driver Strength Control by Full Strength or 1/2, 1/4, 1/8 of Full Strength
  • LVCMOS compatible inputs/outputs

概觀

The IS43/46LR16800F is 134,217,728 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 2,097,152 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 16-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS.