規格 8Mx8
電壓 2.7-3.6V
速度(MHz) 100
腳位/封裝 BGA(24)
狀態 Prod
產品系列 67 = 車規Pseudo SRAM
電壓範圍 BLL = 2.2V (2.4V/2.5V) to 3.6V
焊接 L = 無鉛
温規 A1 = 車規 (-40C to +85°C)

IS67WVH8M8BLL-100B1LA1 特徵

  • 3.0V I/O, 11 bus signals
    • Single ended clock (CK)
  • 1.8V I/O, 12 bus signals
    • Differential clock (CK, CK#)
  • Chip Select (CS#)
  • 8-bit data bus (DQ[7:0])
  • Read-Write Data Strobe (RWDS)
    • Bidirectional Data Strobe / Mask
    • Output at the start of all transactions to indicate refresh latency
    • Output during read transactions as Read Data Strobe
    • Input during write transactions as Write Data Mask RESET# CS# CK CK# VCC VCCQ DQ[7:0] RWDS VSS VSSQ High Performance
  • Up to 333MB/s
  • Double-Data Rate (DDR) - two data transfers per clock
  • 166-MHz clock rate (333 MB/s) at 1.8V VCC
  • 100-MHz clock rate (200 MB/s) at 3.0V VCC
  • Sequential burst transactions
  • Configurable Burst Characteristics
    • Wrapped burst lengths:
    • 16 bytes (8 clocks)
    • 32 bytes (16 clocks)
    • 64 bytes (32 clocks)
    • 128 bytes (64 clocks)
    • Linear burst
    • Hybrid option - one wrapped burst followed by linear burst
    • Wrapped or linear burst type selected in each transaction
    • Configurable output drive strength


The IS66/67WVH8M8ALL/BLL are integrated memory device containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 8M words by 8 bits. The device supports a HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation, designed specially for Mobile and Automotive applications.