類型 Multi I/O SPI, QPI, DTR
電壓 1.65-1.95V
频率 50M/133Mhz
温規 -40 to 125°C
腳位/封裝 T = 8 pin USON (4x3mm)
狀態 S=NOW
產品系列 P = Single/Dual/Quad/QPI SPI
硅片版本 First Rev
特殊選項 J = 標準
焊接 L = 無鉛(無鉛)和無鹵素(符合RoHS)

IS25WP016-JTLE1 特徵

  • Industry Standard Serial Interface
  • - IS25WP016: 16Mbit/2Mbyte - IS25WP080: 8Mbit/1Mbyte - IS25WP040: 4Mbit/512Kbyte - IS25WP020: 2Mbit/256Kbyte - 256 bytes per Programmable Page - Supports standard SPI, Fast, Dual, Dual I/O, Quad, Quad I/O, SPI DTR, Dual I/O DTR, Quad I/O DTR, and QPI - Supports Serial Flash Discoverable Parameters (SFDP)
  • High Performance Serial Flash (SPI)
  • - 50MHz Normal and 133Mhz Fast Read - 532 MHz equivalent QPI - DTR (Dual Transfer Rate) up to 66MHz - Selectable Dummy Cycles - Configurable Drive Strength - Supports SPI Modes 0 and 3 - More than 100,000 Erase/Program cycles - More than 20-year Data Retention
  • Flexible & Efficient Memory Architecture
  • - Chip Erase with Uniform: Sector/Block Erase (4/32/64 Kbyte) - Program 1 to 256 Bytes per Page - Program/Erase Suspend & Resume
  • Efficient Read and Program modes
  • - Low Instruction Overhead Operations - Continuous Read 8/16/32/64-Byte Burst Wrap - Selectable Burst Length - QPI for Reduced Instruction Overhead - AutoBoot Operation
  • Low Power with Wide Temp. Ranges
  • - Single 1.65V to 1.95V Voltage Supply - 10 mA Active Read Current (typ.) - 8 µA Standby Current (typ.) - 1 µA Deep Power Down(typ.) - Temp Grades: Extended: -40°C to +105°C Extended+: -40°C to +125°C Auto Grade: up to +125°C Note: Extended+ should not be used for Automotive.
  • Advanced Security Protection
  • - Software and Hardware Write Protection - Power Supply Lock Protection - 4x256-Byte Dedicated Security Area with OTP User-lockable Bits - 128 bit Unique ID for Each Device (Call Factory)

概觀

The IS25WP016/080/040/020 Serial Flash memory offers a versatile storage solution with high flexibility and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash is for systems that require limited space, a low pin count, and low power consumption. The device is accessed through a 4- wire SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions). The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) which equates to 66Mbytes/s of data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate) commands that transfer addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP (execute in place) operation. The memory array is organized into programmable pages of 256-bytes. This family supports page program mode where 1 to 256 bytes of data are programmed in a single command. QPI (Quad Peripheral Interface) supports 2-cycle instruction further reducing instruction times. Pages can be erased in groups of 4Kbyte sectors, 32Kbyte blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications requiring solid data retention. GLOSSARY Standard SPI In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions, addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check the status of the device. This device supports SPI bus operation modes (0,0) and (1,1). Mutil I/O SPI Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI mode will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations. QPI The device supports Quad Peripheral Interface (QPI) operations only when the device is switched from Standard/Dual/Quad SPI mode to QPI mode using the enter QPI (35h) instruction. The typical SPI protocol requires that the byte-long instruction code being shifted into the device only via SI pin in eight serial clocks. The QPI mode utilizes all four I/O pins to input the instruction code thus requiring only two serial clocks. This can significantly reduce the SPI instruction overhead and improve system performance. Only QPI mode or SPI/Dual/Quad mode can be active at any given time. Enter QPI (35h) and Exit QPI (F5h) instructions are used to switch between these two modes, regardless of the non-volatile Quad Enable (QE) bit status in the Status Register. Power Reset or Hardware/Software Reset will return the device into the standard SPI mode. SI and SO pins become bidirectional I/O0 and I/O1, and WP# and HOLD# pins become I/O2 and I/O3 respectively during QPI mode. DTR In addition to SPI and QPI features, the device also supports Fast READ DTR operation. DTR operation allows high data throughput while running at lower clock frequencies. Fast READ DTR operation uses both rising and falling edges of the clock for address inputs, and data outputs, resulting in reducing input and output cycles by half.