容量 128M
類型 Multi I/O SPI, QPI, DTR
電壓 2.3-3.6V
频率 50M/133Mhz
温規 -40 to 125°C
腳位/封裝 K = 8 pin WSON (6x5 mm)
狀態 Prod
備註 Application Note 
產品系列 P = Single/Dual/Quad/QPI SPI
硅片版本 B
特殊選項 J = 標準
焊接 L = 無鉛(無鉛)和無鹵素(符合RoHS)
相關IC编號
IS25LP128B-JKLE1-TR
IS25LP128-JBLA
IS25LP128-JBLA-TR
IS25LP128-JBLE
IS25LP128-JBLE-TR
IS25LP128-JBLE1
IS25LP128-JBLE1-TR
IS25LP128-JFLA
IS25LP128-JFLA-TR
IS25LP128-JFLE
IS25LP128-JFLE-TR
IS25LP128-JFLE1
IS25LP128-JFLE1-TR
IS25LP128-JGLA
IS25LP128-JGLA-TR
IS25LP128-JGLE
IS25LP128-JGLE-TR
IS25LP128-JGLE1
IS25LP128-JGLE1-TR
IS25LP128-JHLA
IS25LP128-JHLA-TR
IS25LP128-JHLE
IS25LP128-JHLE-TR
IS25LP128-JHLE1
IS25LP128-JHLE1-TR
IS25LP128-JKLA
IS25LP128-JKLA-TR
IS25LP128-JKLE
IS25LP128-JKLE-TR
IS25LP128-JKLE1
IS25LP128-JKLE1-TR
IS25LP128-JLLA
IS25LP128-JLLA-TR
IS25LP128-JLLE
IS25LP128-JLLE-TR
IS25LP128-JLLE1
IS25LP128-JLLE1-TR
IS25LP128-JMLA
IS25LP128-JMLA-TR
IS25LP128-JMLE
IS25LP128-JMLE-TR
IS25LP128-JMLE1
IS25LP128-JMLE1-TR
IS25LP128-JWLE
IS25LP128-JWLE-TR
IS25LP128-QBLA
IS25LP128-QBLA-TR
IS25LP128-QBLE
IS25LP128-QBLE-TR
IS25LP128-QBLE1
IS25LP128-QBLE1-TR
IS25LP128-QFLA
IS25LP128-QFLA-TR
IS25LP128-QFLE
IS25LP128-QFLE-TR
IS25LP128-QFLE1
IS25LP128-QFLE1-TR
IS25LP128-QGLA
IS25LP128-QGLA-TR
IS25LP128-QGLE
IS25LP128-QGLE-TR
IS25LP128-QGLE1
IS25LP128-QGLE1-TR
IS25LP128-QHLA
IS25LP128-QHLA-TR
IS25LP128-QHLE
IS25LP128-QHLE-TR
IS25LP128-QHLE1
IS25LP128-QHLE1-TR
IS25LP128-QKLA
IS25LP128-QKLA-TR
IS25LP128-QKLE
IS25LP128-QKLE-TR
IS25LP128-QKLE1
IS25LP128-QKLE1-TR
IS25LP128-QLLA
IS25LP128-QLLA-TR
IS25LP128-QLLE
IS25LP128-QLLE-TR
IS25LP128-QLLE1
IS25LP128-QLLE1-TR
IS25LP128-QMLA
IS25LP128-QMLA-TR
IS25LP128-QMLE
IS25LP128-QMLE-TR
IS25LP128-QMLE1
IS25LP128-QMLE1-TR
IS25LP128B-JBLA
IS25LP128B-JBLA-TR
IS25LP128B-JBLE
IS25LP128B-JBLE-TR
IS25LP128B-JBLE1
IS25LP128B-JBLE1-TR
IS25LP128B-JFLA
IS25LP128B-JFLA-TR
IS25LP128B-JFLE
IS25LP128B-JFLE-TR
IS25LP128B-JFLE1
IS25LP128B-JFLE1-TR
IS25LP128B-JGLA
IS25LP128B-JGLA-TR
IS25LP128B-JGLE
IS25LP128B-JGLE-TR
IS25LP128B-JGLE1
IS25LP128B-JGLE1-TR
IS25LP128B-JHLA
IS25LP128B-JHLA-TR
IS25LP128B-JHLE
IS25LP128B-JHLE-TR
IS25LP128B-JHLE1
IS25LP128B-JHLE1-TR
IS25LP128B-JKLA
IS25LP128B-JKLA-TR
IS25LP128B-JKLE
IS25LP128B-JKLE-TR
IS25LP128B-JLLA
IS25LP128B-JLLA-TR
IS25LP128B-JLLE
IS25LP128B-JLLE-TR
IS25LP128B-JLLE1
IS25LP128B-JLLE1-TR
IS25LP128B-JMLA
IS25LP128B-JMLA-TR
IS25LP128B-JMLE
IS25LP128B-JMLE-TR
IS25LP128B-JMLE1
IS25LP128B-JMLE1-TR
IS25LP128B-JWLE
IS25LP128B-JWLE-TR
IS25LP128B-QBLA
IS25LP128B-QBLA-TR
IS25LP128B-QBLE
IS25LP128B-QBLE-TR
IS25LP128B-QBLE1
IS25LP128B-QBLE1-TR
IS25LP128B-QFLA
IS25LP128B-QFLA-TR
IS25LP128B-QFLE
IS25LP128B-QFLE-TR
IS25LP128B-QFLE1
IS25LP128B-QFLE1-TR
IS25LP128B-QGLA
IS25LP128B-QGLA-TR
IS25LP128B-QGLE
IS25LP128B-QGLE-TR
IS25LP128B-QGLE1
IS25LP128B-QGLE1-TR
IS25LP128B-QHLA
IS25LP128B-QHLA-TR
IS25LP128B-QHLE
IS25LP128B-QHLE-TR
IS25LP128B-QHLE1
IS25LP128B-QHLE1-TR
IS25LP128B-QKLA
IS25LP128B-QKLA-TR
IS25LP128B-QKLE
IS25LP128B-QKLE-TR
IS25LP128B-QKLE1
IS25LP128B-QKLE1-TR
IS25LP128B-QLLA
IS25LP128B-QLLA-TR
IS25LP128B-QLLE
IS25LP128B-QLLE-TR
IS25LP128B-QLLE1
IS25LP128B-QLLE1-TR
IS25LP128B-QMLA
IS25LP128B-QMLA-TR
IS25LP128B-QMLE
IS25LP128B-QMLE-TR
IS25LP128B-QMLE1
IS25LP128B-QMLE1-TR


IS25LP128B-JKLE1 特徵

  • Industry Standard Serial Interface
  • Low Power with Wide Temp. Ranges
  • - IS25LP128: 128Mbit/16Mbyte - 256 bytes per Programmable Page - Supports standard SPI, Fast, Dual, Dual I/O, Quad I/O, SPI DTR, Dual I/O DTR, Quad I/O DTR, and QPI - Double Transfer Rate (DTR) option - Supports Serial Flash Discoverable Parameters (SFDP)
  • High Performance Serial Flash (SPI)
  • - 133Mhz Fast Read at Vcc=2.7V to 3.6V - 104Mhz Fast Read at Vcc=2.3V to 3.6V - 532MHz equivalent at QPI operation - 50MHz Normal Read - DTR (Dual Transfer Rate) up to 66MHz - Selectable dummy cycles - Configurable drive strength - Supports SPI Modes 0 and 3 - More than 100,000 erase/program cycles - More than 20-year data retention
  • Flexible & Efficient Memory Architecture
  • - Chip Erase with Uniform Sector/Block Erase (4/32/64 Kbyte) - Program 1 to 256 bytes per page - Program/Erase Suspend & Resume
  • Efficient Read and Program modes
  • - Low Instruction Overhead Operations - Continuous Read 8/16/32/64-Byte Burst Wrap - Selectable burst length - QPI for reduced instruction overhead - Single 2.3V to 3.6V Voltage Supply - 5 mA Active Read Current - 10 µA Standby Current - 5 µA Deep Power Down - Temp Grades: Extended: -40°C to +105°C Extended+: -40°C to +125°C(1) (Call Factory) Auto Grade: up to +125°C Note: 1. Extended+ should not be used for Automotive.
  • Advanced Security Protection
  • - Software and Hardware Write Protection - Power Supply lock protect - 4x256-Byte dedicated security area with OTP user-lockable bits - 128 bit Unique ID for each device (Call Factory)

概觀

The IS25LP128 Serial Flash memory offers a versatile storage solution with high flexibility and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash are for systems that require limited space, a low pin count, and low power consumption. The device is accessed through a 4-wire SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions). The device supports Dual and Quad I/O as well as standard and Dual Output SPI. Clock frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) which equates to 66Mbytes/s of data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate) commands that transfer addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP (execute in place) operation. The memory array is organized into programmable pages of 256-bytes. This family supports page program mode where 1 to 256 bytes of data are programmed in a single command. QPI (Quad Peripheral Interface) supports 2- cycle instruction further reducing instruction times. Pages can be erased in groups of 4Kbyte sectors, 32Kbyte blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications requiring solid data retention. GLOSSARY Standard SPI In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions, addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check the status of the device. This device supports SPI bus operation modes (0,0) and (1,1). Multi I/O SPI Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI mode will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations. QPI The device supports Quad Peripheral Interface (QPI) operations only when the device is switched from Standard/Dual/Quad SPI mode to QPI mode using the enter QPI (35h) instruction. The typical SPI protocol requires that the byte-long instruction code being shifted into the device only via SI pin in eight serial clocks. The QPI mode utilizes all four I/O pins to input the instruction code thus requiring only two serial clocks. This can significantly reduce the SPI instruction overhead and improve system performance. Only QPI mode or SPI/Dual/Quad mode can be active at any given time. Enter QPI (35h) and Exit QPI (F5h) instructions are used to switch between these two modes, regardless of the non-volatile Quad Enable (QE) bit status in the Status Register. Power Reset or Hardware/Software Reset will return the device into the standard SPI mode. SI and SO pins become bidirectional I/O0 and I/O1, and WP# and HOLD# pins become I/O2 and I/O3 respectively during QPI mode. DTR In addition to SPI and QPI features, the device also supports Fast READ DTR operation, which allows high data throughput while running at lower clock frequencies. DTR READ mode uses both rising and falling edges of the clock to drive output, resulting in reducing input and output cycles by half.