1. ISSI
  2. SRAM
  3. Synchronous SRAM
  4. Pipeline
  5. 2.5V
  6. TQFP
  7. IS61VPS51236A-250TQ-TR

  IS61VPS51236A-250TQ-TR

Datasheet
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Org 512Kx36
Pkg(Pins) TQFP
tKQ 2.6, 3.1
Vcc 2.5V
VccQ 2.5V
Models IBIS, BSDL
Solder SnPb
Status Prod
Comment P/SCD
Outpack Tape on reel
Speed(Mhz) 250
Temp.Range Commercial Grade (0C to +70°C)
Product Family High Speed
Datasheet
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IS61VPS51236A-250TQ-TR Features

  • Internal self-timed write cycle
  • Individual Byte Write Control and Global Write
  • Clock controlled, registered address, data and control
  • Burst sequence control using MODE input
  • Three chip enable option for simple depth ex- pansion and address pipelining
  • Common data inputs and data outputs
  • Auto Power-down during deselect
  • Single cycle deselect
  • Snooze MODE for reduced-power standby
  • JTAG Boundary Scan for PBGA package
  • Power Supply LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VPS: Vdd 2.5V + 5%, Vddq 2.5V + 5%
  • JEDEC 100-Pin TQFP, 119-ball PBGA, 165-ball PBGA, and 209-ball (x72) packages

Overview

The ISSI IS61LPS/VPS51236A, IS61LPS/VPS102418A, and IS61LPS/VPS25672A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and network- ing applications. The IS61LPS/VPS51236A is organized as 524,288 words by 36 bits, the IS61LPS/VPS102418A is organized as 1,048,576 words by 18 bits, and the IS61LPS/ VPS25672A is organized as 262,144 words by 72 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single mono- lithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.