1. ISSI
  2. SRAM
  3. Synchronous SRAM
  4. No-Wait(ZBT)
  5. 3.3V
  6. 72M 2Mx36
  7. TQFP
  8. IS61NVVP409618B-166TQ

  IS61NVVP409618B-166TQ

Datasheet
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Density 72M
Org 2Mx36
Pkg(Pins) TQFP
tKQ 2.6, 3.1, 3.5
Vcc 3.3V
VccQ 2.5/3.3V
Solder SnPb
Status Prod
Comment P
Speed(Mhz) 166
Temp.Range Commercial Grade (0C to +70°C)
Product Family High Speed
Datasheet
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IS61NVVP409618B-166TQ Features

  • 100 percent bus utilization
  • No wait cycles between Read and Write
  • Internal self-timed write cycle
  • Individual Byte Write Control
  • Single R/W (Read/Write) control pin
  • Clock controlled, registered address, data and control
  • Interleaved or linear burst sequence control us- ing MODE input
  • Three chip enables for simple depth expansion and address pipelining
  • Power Down mode
  • Common data inputs and data outputs
  • CKE pin to enable clock and suspend operation
  • JEDEC 100-pin TQFP, 165-ball PBGA and 119- ball PBGA packages
  • Power supply: NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NVVP: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)
  • JTAG Boundary Scan for PBGA packages
  • Industrial temperature available

Overview

, 100 percent bus utilization , No wait cycles between Read and Write , Internal self-timed write cycle , Individual Byte Write Control , Single R/W (Read/Write) control pin , Clock controlled, registered address,