IS61NVVF409618B-7-TR
Features
-
100 percent bus utilization
-
No wait cycles between Read and Write
Internal self-timed write cycle
-
Individual Byte Write Control
-
Single Read/Write control pin
-
Clock controlled, registered address,
-
data and control
Interleaved or linear burst sequence control us-
ing MODE input
-
Three chip enables for simple depth expansion
and address pipelining
-
Power Down mode
-
Common data inputs and data outputs
-
CKE pin to enable clock and suspend operation
-
JEDEC 100-pin TQFP, 119-ball PBGA, and 165-
ball PBGA packages
-
Power supply:
NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%)
NVVF: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)
-
JTAG Boundary Scan for PBGA packages