1. ISSI
  2. SRAM
  3. Synchronous SRAM
  4. No-Wait(ZBT)
  5. 1.8V
  6. 36M 2Mx18
  7. QFP(100), BGA(165, 119)
  8. IS61NVVF204818B-7-TR

  IS61NVVF204818B-7-TR

Datasheet
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Density 36M
Org 2Mx18
Vcc 1.8V
VccQ 1.8V
Status Prod
tKQ(ns) 6.5, 7.5
Pkg Pins QFP(100), BGA(165, 119)
Speed Mhz 133, 117
Comment Prev Rev F
Datasheet
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IS61NVVF204818B-7-TR Features

  • 100 percent bus utilization
  • No wait cycles between Read and Write Internal self-timed write cycle
  • Individual Byte Write Control
  • Single Read/Write control pin
  • Clock controlled, registered address,
  • data and control Interleaved or linear burst sequence control us- ing MODE input
  • Three chip enables for simple depth expansion and address pipelining
  • Power Down mode
  • Common data inputs and data outputs
  • CKE pin to enable clock and suspend operation
  • JEDEC 100-pin TQFP, 119-ball PBGA, and 165- ball PBGA packages
  • Power supply: NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NVVF: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)
  • JTAG Boundary Scan for PBGA packages

Overview

, 100 percent bus utilization , No wait cycles between Read and Write Internal self-timed write cycle , , Individual Byte Write Control , Single Read/Write control pin , Clock controlled, registered address,

 

Related Part Number(s)

Description Stock Qty Available Qty Description Stock Qty Available Qty
IS61NVVF204818B-7 IS61NVVF204818B