1. ISSI
  2. SRAM
  3. Synchronous SRAM
  4. No-Wait(ZBT)
  5. 2.5V
  6. 36M 2Mx18
  7. QFP(100), BGA(165, 119)
  8. IS61NVP204818B-200B2I-TR

  IS61NVP204818B-200B2I-TR

Datasheet
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Density 36M
Org 2Mx18
Vcc 2.5V
VccQ 2.5V
Status Prod
tKQ(ns) 2.6, 3.1, 3.5
Pkg Pins QFP(100), BGA(165, 119)
Speed Mhz 250, 200, 166
Comment Prev Rev P, IS61NVP204818A
Datasheet
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IS61NVP204818B-200B2I-TR Features

  • 100 percent bus utilization
  • No wait cycles between Read and Write
  • Single R/W (Read/Write) control pin
  • Clock controlled, registered address, Internal self-timed write cycle Individual Byte Write Control
  • data and control Interleaved or linear burst sequence control us- ing MODE input
  • Three chip enables for simple depth expansion and address pipelining
  • Power Down mode
  • Common data inputs and data outputs
  • CKE pin to enable clock and suspend operation
  • JEDEC 100-pin TQFP, 165-ball PBGA and 119- ball PBGA packages
  • Power supply: NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NVVP: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)
  • JTAG Boundary Scan for PBGA packages

Overview

, 100 percent bus utilization , No wait cycles between Read and Write , , , Single R/W (Read/Write) control pin , Clock controlled, registered address,

 

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IS61NVP204818B-166TQ IS61NVP204818B-200TQI-TR
IS61NVP204818B-166TQ-TR IS61NVP204818B-200TQL
IS61NVP204818B-166TQI IS61NVP204818B-200TQL-TR
IS61NVP204818B-166TQI-TR IS61NVP204818B-200TQLI 72
IS61NVP204818B-166TQL IS61NVP204818B-200TQLI-TR
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