IS61NLP51218B-200B2I

Density	9M
Org	512Kx18
Vcc	3.3V
VccQ	2.5/3.3V
Status	Prod
tKQ(ns)	2.6, 3.1
Pkg Pins	BGA(119), QFP(100), BGA(165)
Speed Mhz	250, 200
Comment Prev Rev	P, IS61NLP51218A

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IS61NLP51218B-200B2I Features

100 percent bus utilization
No wait cycles between Read and Write
Internal self-timed write cycle
Individual Byte Write Control
Single R/W (Read/Write) control pin
Clock controlled, registered address, data and control
Interleaved or linear burst sequence control us- ing MODE input
Three chip enables for simple depth expansion and address pipelining
Power Down mode
Common data inputs and data outputs
CKE pin to enable clock and suspend operation
JEDEC 100-pin QFP, 165-ball BGA and 119-ball BGA packages
Power supply: NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NVVP: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)
JTAG Boundary Scan for BGA packages
Industrial temperature available

Overview

, 100 percent bus utilization , No wait cycles between Read and Write , Internal self-timed write cycle , Individual Byte Write Control , Single R/W (Read/Write) control pin , Clock controlled, registered address,

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IS61NLP51218B-200B2I-TR

IS61NLP51218B-250B2-TR

IS61NLP51218B-200B2

IS61NLP51218B-250B2I

IS61NLP51218B-200B2-TR

IS61NLP51218B-250B2I-TR