IS61NLP409618B-200B2I

Density	72M
Org	4Mx18
Vcc	3.3V
VccQ	2.5/3.3V
Status	Prod
tKQ(ns)	2.6, 3.1, 3.5
Pkg Pins	QFP(100), BGA(165, 119)
Speed Mhz	250, 200, 166
Comment Prev Rev	P

Density

72M

Org

4Mx18

Vcc

3.3V

VccQ

2.5/3.3V

Status

Prod

tKQ(ns)

2.6, 3.1, 3.5

Pkg Pins

QFP(100), BGA(165, 119)

Speed Mhz

250, 200, 166

Comment Prev Rev

IS61NLP409618B-200B2I Features

100 percent bus utilization
No wait cycles between Read and Write
Internal self-timed write cycle
Individual Byte Write Control
Single R/W (Read/Write) control pin
Clock controlled, registered address, data and control
Interleaved or linear burst sequence control us- ing MODE input
Three chip enables for simple depth expansion and address pipelining
Power Down mode
Common data inputs and data outputs
CKE pin to enable clock and suspend operation
JEDEC 100-pin TQFP, 165-ball PBGA and 119- ball PBGA packages
Power supply: NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NVVP: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)
JTAG Boundary Scan for PBGA packages
Industrial temperature available

Overview

, 100 percent bus utilization , No wait cycles between Read and Write , Internal self-timed write cycle , Individual Byte Write Control , Single R/W (Read/Write) control pin , Clock controlled, registered address,

Description

Stock Qty

Available Qty

Description

Stock Qty

Available Qty

IS61NLP409618B-200B2I-TR

IS61NLP409618B-166TQL

IS61NLP409618B-166B2

IS61NLP409618B-166TQL-TR

IS61NLP409618B-166B2-TR

IS61NLP409618B-166TQLI