-
ISSI
-
SRAM
-
Synchronous SRAM
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No-Wait(ZBT)
-
3.3V
-
72M 4Mx18
-
QFP(100), BGA(165, 119)
-
IS61NLF409618B
|
Density
|
72M
|
|
Org
|
4Mx18
|
|
Vcc
|
3.3V
|
|
VccQ
|
2.5/3.3V
|
|
Status
|
Prod
|
|
tKQ(ns)
|
6.5, 7.5
|
|
Pkg Pins
|
QFP(100), BGA(165, 119)
|
|
Speed Mhz
|
133, 117
|
|
Comment Prev Rev
|
F
|
IS61NLF409618B
Features
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100 percent bus utilization
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No wait cycles between Read and Write
Internal self-timed write cycle
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Individual Byte Write Control
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Single Read/Write control pin
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Clock controlled, registered address,
-
data and control
Interleaved or linear burst sequence control us-
ing MODE input
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Three chip enables for simple depth expansion
and address pipelining
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Power Down mode
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Common data inputs and data outputs
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CKE pin to enable clock and suspend operation
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JEDEC 100-pin TQFP, 119-ball PBGA, and 165-
ball PBGA packages
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Power supply:
NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%)
NVVF: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)
-
JTAG Boundary Scan for PBGA packages