IS61NLF12836A-6

Org 128Kx36
Pkg(Pins) BGA(119), QFP(100), BGA(165)
tKQ 6.5, 7.5
Vcc 3.3V
VccQ 2.5/3.3V
Models IBIS
Status Prod
Comment F
Speed(Mhz) 177, 133

IS61NLF12836A-6 Features

  • 100 percent bus utilization
  • No wait cycles between Read and Write
  • Internal self-timed write cycle
  • Individual Byte Write Control
  • Single Read/Write control pin
  • Clock controlled, registered address, data and control
  • Interleaved or linear burst sequence control us- ing MODE input
  • Three chip enables for simple depth expansion and address pipelining
  • Power Down mode
  • Common data inputs and data outputs
  • CKE pin to enable clock and suspend operation
  • JEDEC 100-pin TQFP, 119-ball PBGA, and 165- ball PBGA packages
  • Power supply: NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
  • Industrial temperature available