1. ISSI
  2. SRAM
  3. Synchronous SRAM
  4. Pipeline
  5. 3.3V
  6. 9M 256Kx32
  7. QFP(100)
  8. IS61LPS25632B-200TQLI-TR

  IS61LPS25632B-200TQLI-TR

Datasheet
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Density 9M
Org 256Kx32
Vcc 3.3V
VccQ 2.5/3.3V
Status Prod
tKQ(ns) 3.1, 3.8
Pkg Pins QFP(100)
Speed Mhz 200, 166
Comment Prev Rev P/SCD, IS61LPS25632A
Datasheet
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IS61LPS25632B-200TQLI-TR Features

  • Internal self-timed write cycle
  • Individual Byte Write Control and Global Write
  • Clock controlled, registered address, data and control
  • Burst sequence control using MODE input
  • Three chip enable option for simple depth ex- pansion and address pipelining
  • Common data inputs and data outputs
  • Auto Power-down during deselect
  • Single cycle deselect
  • Snooze MODE for reduced-power standby
  • JTAG Boundary Scan for BGA package
  • Power Supply LPS: Vdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%) VPS: Vdd 2.5V (+ 5%), Vddq 2.5V (+ 5%) VVPS: Vdd 1.8V (+ 5%), Vddq 1.8V (+ 5%)
  • JEDEC 100-Pin QFP, 119-ball BGA, and 165- ball BGA packages

Overview

The 9Mb product family features high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and net- working applications. The IS61LPS/VPS25636B and IS64LPS25636B are organized as 262,144 words by 36 bits. The IS61LPS25632B is organized as 262,144 words by 32 bits. The IS61LPS/VPS51218B is organized as 524,288 words by 18 bits. Fabricated with ISSI's ad- vanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.

 

Related Part Number(s)

Description Stock Qty Available Qty
IS61LPS25632B-200TQLI