IS45S32200L-7TLA2

Density 64M
Org 2Mx32
Vcc 3.3V
Type SDR
Refresh 4K
Speed 7 = 143MHz
Status Prod
Comment
Pkg Pins TSOP2(86), BGA(90)
Temp. Grade A2 = Automotive Grade (-40°C to +105°C)
Solder Type L = 100% matte Sn
Generation L = L
Number Of Words 200 = 2M
Operating Voltage Range S = 3.3V SDR
Bus Width 32 = x32
Package Type T = TSOP
Product Family 45 = SDR Automotive grade

IS45S32200L-7TLA2 Features

  • Clock frequency: 200, 166, 143, 133 MHz
  • Fully synchronous; all signals referenced to a positive clock edge
  • Internal bank for hiding row access/precharge
  • Single 3.3V power supply
  • LVTTL interface
  • Programmable burst length: (1, 2, 4, 8, full page)
  • Programmable burst sequence: Sequential/Interleave
  • Self refresh modes
  • 4096 refresh cycles every 16ms (A2 grade) or 64ms (Commercia, Industrial, A1 grade)
  • Random column address every clock cycle
  • Programmable CAS latency (2, 3 clocks)
  • Burst read/write and burst read/single write operations capability
  • Burst termination by burst stop and precharge command OPTIONS
  • Packages: 86-pin TSOP-II 90-ball TF-BGA

Overview

ISSI's 64Mb Synchronous DRAM IS42/45S32200L is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.

 

Related Part Number(s)

Description Stock Qty Available Qty Description Stock Qty Available Qty
IS45S32200L-7TLA2-TR 6,500 IS45S32200L-7BA1-TR
IS45S32200L IS45S32200L-7BLA1 6,951
IS45S32200L-6BLA1 6,997 IS45S32200L-7BLA1-TR 7,500
IS45S32200L-6BLA1-TR 7,500 IS45S32200L-7BLA2 60
IS45S32200L-6TLA1 6,440 IS45S32200L-7BLA2-TR 5,000
IS45S32200L-6TLA1-TR 6,500 IS45S32200L-7TLA1 10,800
IS45S32200L-7BA1 IS45S32200L-7TLA1-TR 6,500